AD9752-EB Analog Devices Inc, AD9752-EB Datasheet
AD9752-EB
Specifications of AD9752-EB
Related parts for AD9752-EB
AD9752-EB Summary of contents
Page 1
... BiCMOS devices. 3. On-chip, edge-triggered input CMOS latches interface readily to +2 CMOS logic families. The AD9752 can support update rates up to 125 MSPS flexible single-supply operating range of 4 5.5 V and a wide full-scale current adjustment span allow the AD9752 to operate at reduced power levels ...
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... AD9752–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL + MIN MAX Differential Nonlinearity (DNL + MIN MAX ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) 2 Full-Scale Output Current Output Compliance Range Output Resistance ...
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... Differential Transformer Coupled Output, OUTFS Typ Max 2.5 2 –82 –74 –76 – AD9752 Units MSPS pA/ Hz pA/ Hz dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc ...
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... ST OR 0.1% Figure 1. Timing Diagram Max Units Model +6.5 V AD9752AR +6.5 V AD9752ARU – +85 C 28-Lead TSSOP +0.3 V AD9752-EB +6.5 V DVDD + 0 Small Outline IC Thin Shrink Small Outline Package. DVDD + 0.3 V THERMAL CHARACTERISTICS AVDD + 0.3 V Thermal Resistance AVDD + 0.3 V 28-Lead 300 Mil SOIC AVDD + 0 ...
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... DB10 2 27 DVDD DB9 3 26 DCOM 4 DB8 25 NC DB7 5 24 AVDD AD9752 DB6 6 23 ICOMP TOP VIEW (Not to Scale) DB5 7 22 IOUTA DB4 8 21 IOUTB DB3 9 ACOM 20 DB2 DB1 ADJ 12 DB0 17 REFIO REFLO SLEEP CONNECT PIN FUNCTION DESCRIPTIONS –5– AD9752 ...
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... It is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone For MIN MAX +5V REFLO AVDD ACOM 150pF AD9752 PMOS ICOMP CURRENT SOURCE ARRAY IOUTA SEGMENTED SWITCHES LSB IOUTB FOR DB11–DB3 SWITCHES LATCHES ...
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... A – dBFS OUT Figure 10. Single-Tone SFDR vs OUT OUT CLOCK –7– AD9752 = +25 C, SFDR up to Nyquist, unless otherwise noted 0dBFS –6dBFS 70 60 –12dBFS – MHz OUT Figure 5. SFDR vs. f OUT 90 10mA FS ...
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... AD9752 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 –0.1 –0.2 –0.3 –0.4 0 1000 2000 3000 4000 CODE Figure 12. Typical INL 125MSPS CLK – 13.5MHz OUT1 – 14.5MHz OUT2 A = 0dBFS OUT –30 SFDR = 68.4dBc –40 –50 –60 –70 –80 –90 –100 ...
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... CLOCK FUNCTIONAL DESCRIPTION Figure 17 shows a simplified block diagram of the AD9752. The AD9752 consists of a large PMOS current source array that is capable of providing total current. The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits or middle bits consist of 15 equal current sources whose value is 1/16th of an MSB current source ...
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... Figure 19. External Reference Configuration AVDD 1.2V AD1580 REFERENCE CONTROL AMPLIFIER The AD9752 also contains an internal control amplifier that is used to regulate the DAC’s full-scale output current, I The control amplifier is configured as a V-I converter as shown in Figure 19, such that its current output, I the ratio of the V in Equation 4 ...
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... V is set by the breakdown limits of the CMOS process. SET Operation beyond this maximum limit may result in a break- down of the output stage and affect the reliability of the AD9752 The positive output compliance range is slightly dependent on GC the full-scale output current not exceed 62 ...
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... The drivers of the digital data interface circuitry should be specified to meet the mini- mum setup and hold times of the AD9752 as well as its re- quired min/max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above con- ditions will result in the lowest data feedthrough and noise ...
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... SLEEP MODE OPERATION The AD9752 has a power-down function which turns off the output current and reduces the supply current to less than 8.5 mA over the specified supply range of 2 5.5 V and temperature range. This mode can be activated by applying a logic level “1” to the SLEEP pin. This digital input also con- tains an active pull-down circuit that ensures the AD9752 re- mains enabled if this input is left disconnected ...
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... In this case, AVDD which is the positive analog supply for both the AD9752 and the op amp is also used to level-shift the differ- ential output of the AD9752 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. ...
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... PSRR of the DAC at 1 MHz which Figure 33 becomes Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9752 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system ...
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... MHz which is represented in Figure 35b. In both cases, the spurious free range between the transmitted tones and the empty bins is greater than 60 dB. Using the AD9752 for Quadrature Amplitude Modulation (QAM) QAM is one of the most widely used digital modulation schemes in digital communication systems. This modulation technique can be found in FDM as well as spreadspectrum (i ...
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... DAC. The differential voltage outputs of U1 and U2 are fed into the respective differential inputs of the AD8346 via matching networks. Using the same matching techniques described above, Figure 38 shows an example of the AD9752 used in a W-CDMA transmit- ter application using the AD6122 CDMA 3 V transmitter IF REFLO REFIO AD9752 (“ ...
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... FREQUENCY CU1 AD9752 EVALUATION BOARD General Description The AD9752- evaluation board for the AD9752 12-bit D/A converter. Careful attention to layout and circuit design SPAN 14.096MHz combined with a prototyping area allow the user to easily and effectively evaluate the AD9752 in any application where high resolution, high speed conversion is required ...
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... REV. 0 Figure 41. Evaluation Board Schematic –19– AD9752 ...
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... AD9752 Figure 42. Silkscreen Layer—Top Figure 43. Component Side PCB Layout (Layer 1) –20– REV. 0 ...
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... REV. 0 Figure 44. Ground Plane PCB Layout (Layer 2) Figure 45. Power Plane PCB Layout (Layer 3) –21– AD9752 ...
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... AD9752 Figure 46. Solder Side PCB Layout (Layer 4) Figure 47. Silkscreen Layer—Bottom –22– REV. 0 ...
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... PLANE BSC 0.0091 (0.23) 28-Lead TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60 PIN 1 0.0433 (1.10) MAX 0.0118 (0.30) 0.0256 (0.65) 0.0079 (0.20) BSC 0.0075 (0.19) 0.0035 (0.090) –23– AD9752 0.0291 (0.74) 45 0.0098 (0.25) 0.0500 (1.27 0.0157 (0.40) 0.028 (0.70 0.020 (0.50) ...