AD974AR Analog Devices Inc, AD974AR Datasheet - Page 12

• Manufacturer Part Number: AD974AR
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc
• Type: Data Acquisition System (DAS)r

Specifications of AD974AR

• Package/case: 28-SOIC
• Features: 4?Ch., 200kSPS Data Acquisition System
• Interface Type: Serial
• Number Of Bits: 16
• Number Of Channels: 4
• Mounting Type: Surface Mount
• Rohs Status: RoHS non-compliant
• Resolution (bits): 16 b
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 5V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-AD974CB - BOARD EVAL FOR AD974
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD974
EXTERNAL CONTINUOUS CLOCK DATA READ DURING
CONVERSION WITH SYNC OUTPUT GENERATED
Figure 9 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a continu-
ous external clock with the generation of a SYNC output. What
permits the generation of a SYNC output is a transition of
DATACLK either while CS is high or while both CS and R/C
are low.
With a continuous clock the CS pin cannot be tied low as it
could be with a discontinuous clock. Use of a continuous clock
while a conversion is occurring can increase the DNL and
Transition Noise.
In Figure 9 a conversion is initiated by taking R/C low with CS
held low. While this condition exists a transition of DATACLK,
clock pulse #0, will enable the generation of a SYNC pulse. Less
then 83 ns after R/C is taken low the BUSY output will go low
Figure 9. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion
Using An External Continuous Data Clock (EXT/ INT Set to Logic High)
DATACLK
BUSY
SYNC
DATA
EXT
R/C
CS
t
16
t
13
t
t
2
12
t
14
t
1
0
t
17
t
15
1
t
12
2
–12–
BIT 15
(MSB)
t
18
to indicate that the conversion process has began. Figure 9
shows R/C then going high and after a delay of greater than
15 ns (t
SYNC output. The SYNC output will appear approximately
50 ns after this rising edge and will be valid on the falling edge
of clock pulse #1 and the rising edge of clock pulse #2. The
MSB will be valid approximately 40 ns after the rising edge of
clock pulse #2 and can be latched off either the falling edge of
clock pulse #2 or the rising edge of clock pulse #3. The LSB
will be valid on the falling edge of clock pulse #17 and the
rising edge of clock pulse #18.
Data should be clocked out during the 1st half of BUSY to
not degrade conversion performance. This requires use of a
10 MHz DATACLK or greater, with data being read out as
soon as the conversion process begins.
3
t
20
15
), clock pulse #1 can be taken high to request the
(LSB)
BIT 0
18
t
t
18
19
REV. A