AD9640ABCPZ-150 Analog Devices Inc, AD9640ABCPZ-150 Datasheet - Page 13

• Manufacturer Part Number: AD9640ABCPZ-150
• Description: 14Bit 150Msps Dual 1.8V PB Free ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9640ABCPZ-150

• Design Resources: Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
• Number Of Bits: 14
• Sampling Rate (per Second): 150M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 938mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Number Of Elements: 2
• Resolution: 14Bit
• Architecture: Pipelined
• Sample Rate: 150MSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±1V
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 1.8V
• Single Supply Voltage (min): 1.7V
• Single Supply Voltage (max): 1.9V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Differential Linearity Error: -0.95LSB/1.5LSB
• Integral Nonlinearity Error: ±5LSB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LFCSP EP
• Input Signal Type: Differential
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SMI SCLK
SMI SDFS
SMI SDO
CLK+
CLK–
CH A/CH B DATA
CH A/CH B FAST
Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode 1 Through Fast Detect Mode 5)
DETECT
DCO+
DCO–
CLK+
CLK–
t
CSSCLK
SYNC
CLK+
t
SSCLKSDFS
A
A
N – 13
N – 7
Figure 5. Signal Monitor SPORT Output Timing (Divide by 2 Mode)
N
B
B
t
t
A
PD
A
A
N – 12
N – 6
N + 1
t
CLK
t
B
B
SSYNC
Figure 4. SYNC Input Timing Requirements
A
A
N – 11
N – 5
N + 2
B
B
Rev. B | Page 13 of 52
A
A
N – 10
N – 4
N + 3
B
B
t
HSYNC
A
A
N – 9
N – 3
t
N + 4
DCO
t
B
B
SSCLKSDO
A
A
N – 8
N – 2
N + 5
DATA
B
B
A
A
N + 6
N – 7
N – 1
t
CLK
B
B
A
A
N + 7
N – 6
N
B
B
N + 8
A
A
N – 5
N + 1
B
B
A
N – 4
A
N + 2
DATA
AD9640