AD9520-4BCPZ-REEL7 Analog Devices Inc, AD9520-4BCPZ-REEL7 Datasheet - Page 8
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AD9520-4BCPZ-REEL7
Manufacturer Part Number
AD9520-4BCPZ-REEL7
Description
Clock IC With 1.6GHz On-chip VCO
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9520-4BCPZ-REEL7.pdf
(84 pages)
Specifications of AD9520-4BCPZ-REEL7
Design Resources
Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVPECL
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
1.8GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
1.8GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9520-4/PCBZ - BOARD EVAL FOR AD9520-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9520-4
TIMING CHARACTERISTICS
Table 5.
Parameter
LVPECL OUTPUT RISE/FALL TIMES
PROPAGATION DELAY, t
OUTPUT SKEW, LVPECL OUTPUTS
CMOS OUTPUT RISE/FALL TIMES
PROPAGATION DELAY, t
OUTPUT SKEW, CMOS OUTPUTS
OUTPUT SKEW, LVPECL-TO-CMOS OUTPUT
1
The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
Output Rise Time, t
Output Fall Time, t
For All Divide Values
Variation with Temperature
LVPECL Outputs That Share the Same Divider
LVPECL Outputs on Different Dividers
All LVPECL Outputs Across Multiple Parts
CMOS Outputs That Share the Same Divider
All CMOS Outputs on Different Dividers
Output(s) That Share the Same Divider
Output(s) That Are on Different Dividers
All CMOS Outputs Across Multiple Parts
Output Rise Time, t
Output Fall Time, t
Output Rise Time, t
Output Fall Time, t
For All Divide Values
Variation with Temperature
FP
RP
FC
FC
RC
RC
PECL
CMOS
, CLK-TO-LVPECL OUTPUT
, CLK-TO-CMOS OUTPUT
1
1
1
Min
800
2.1
1.18
850
1.20
Rev. 0 | Page 8 of 84
Typ
130
130
1050
970
5
5
5
5
750
715
965
890
2.75
3.35
2
7
10
10
10
1.76
1.0
1.78
Max
170
170
1280
1180
16
20
45
60
190
960
890
1280
1100
3.55
85
105
240
285
600
620
2.48
2.50
Unit
ps
ps
ps
ps
ps/°C
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ps/°C
ps
ps
ps
ps
ps
ps
ns
ns
Test Conditions/Comments
Termination = 50 Ω to VS_DRV − 2 V
20% to 80%, measured differentially (rise/fall
time are independent of VS and are valid for
VS_DRV = 3.3 V and 2.5 V)
80% to 20%, measured differentially (rise/fall
time are independent of VS and are valid for
VS_DRV = 3.3 V and 2.5 V)
High frequency clock distribution configuration
Clock distribution configuration
Termination = open
VS_DRV = 3.3 V
VS_DRV = 2.5 V
VS_DRV = 3.3 V
VS_DRV = 2.5 V
VS_DRV = 3.3 V and 2.5 V
Termination = open
20% to 80%; C
80% to 20%; C
20% to 80%; C
80% to 20%; C
Clock distribution configuration
VS_DRV = 3.3 V
VS_DRV = 2.5 V
VS_DRV = 3.3 V and 2.5 V
VS_DRV = 3.3 V
VS_DRV = 2.5 V
VS_DRV = 3.3 V
VS_DRV = 2.5 V
VS_DRV = 3.3 V
VS_DRV = 2.5 V
All settings identical; different logic type
LVPECL to CMOS on same part
LVPECL to CMOS on same part
LOAD
LOAD
LOAD
LOAD
= 10 pF; VS_DRV = 3.3 V
= 10 pF; VS_DRV = 3.3 V
= 10 pF; VS_DRV = 2.5 V
= 10 pF; VS_DRV = 2.5 V