AD9520-4BCPZ-REEL7 Analog Devices Inc, AD9520-4BCPZ-REEL7 Datasheet - Page 47

• Manufacturer Part Number: AD9520-4BCPZ-REEL7
• Description: Clock IC With 1.6GHz On-chip VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-4BCPZ-REEL7

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 1.8GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9520-4/PCBZ - BOARD EVAL FOR AD9520-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DIVIDER 0
DIVIDER 1
DIVIDER 2
Let
Δ
Δ
T
seconds).
Φ =
16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]
The channel divide by is set as N = high cycles and M = low
cycles.
Case 1
For Φ ≤ 15,
Δ
Δ
Case 2
For Φ ≥ 16,
Δ
Δ
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input
clock cycle. Figure 48 shows the results of setting such a coarse
offset between outputs.
Synchronizing the Outputs—SYNC Function
The AD9520 clock outputs can be synchronized to each other.
Outputs can be individually excluded from synchronization.
Synchronization consists of setting the nonexcluded outputs to
a preset set of static conditions. These conditions include the
divider ratio and phase offsets for a given channel divider. This
allows the user to specify different divide ratios and phase offsets
for each of the four channel dividers. Releasing the SYNC pin
allows the outputs to continue clocking with the preset conditions
applied.
Synchronization of the outputs is executed in several ways:
• The SYNC pin is forced low and then released (manual sync).
• By setting and then resetting any one of the following three
• Synchronization of the outputs can be executed as part of the
DIVIDER INPUT
X
t
c
t
c
t
c
bits: the soft SYNC bit (0x230[0]), the soft reset bit (0x000[5]
[mirrored]), and the power-down distribution reference bit
(0x230[1]).
chip power-up sequence.
= delay (in seconds).
= Φ × T
= (Φ − 16 + M + 1) × T
= delay (in cycles of clock signal at input to D
= Δ
= Δ
= period of the clock signal at the input of the divider, D
CHANNEL
t
t
/T
/T
PO = 0
PO = 1
PO = 2
SH = 0
SH = 0
SH = 0
X
X
X
= Φ
Figure 48. Effect of Coarse Phase Offset (or Delay)
0
1
Tx
2
3
X
1 × Tx
2 × Tx
4
CHANNEL DIVIDER OUTPUTS
5
DIV = 4, DUTY = 50%
6
7
8
9 10 11 12 13 14 15
X
).
X
Rev. 0 | Page 47 of 84
(in
• The RESET pin is forced low and then released (chip reset).
• The PD pin is forced low and then released (chip power-down).
• Whenever a VCO calibration is completed, an internal SYNC
The most common way to execute the SYNC function is to use
the SYNC pin to perform a manual synchronization of the
outputs. This requires a low-going signal on the SYNC pin,
which is held low and then released when synchronization is
desired. The timing of the SYNC operation is shown in
(using the VCO divider) and in
used). There is an uncertainty of up to 1 cycle of the clock at the
input to the channel divider due to the asynchronous nature of
the SYNC signal with respect to the clock edges inside the
AD9520.
The pipeline delay from the SYNC rising edge to the beginning
of the synchronized output clocking is between 14 cycles and
15 cycles of clock at the channel divider input, plus either one
cycle of the VCO divider input (see
the channel divider input (see
the VCO divider is used. Cycles are counted from the rising
edge of the signal. In addition, there is an additional 1.2 ns (typical)
delay from the SYNC signal to the internal synchronization logic,
as well as the propagation delay of the output driver. The driver
propagation delay is approximately 100 ps for the LVPECL
driver and approximately 1.5 ns for the CMOS driver.
Another common way to execute the SYNC function is by
setting and resetting the soft SYNC bit at 0x230[0]. Both setting
and resetting of the soft SYNC bit requires an update all registers
(0x232[0] = 1) operation to take effect.
A SYNC operation brings all outputs that have not been excluded
(by the ignore SYNC bit) to a preset condition before allowing
the outputs to begin clocking in synchronicity. The preset condition
takes into account the settings in each of the channel’s start high
bit and its phase offset. These settings govern both the static state
of each output when the SYNC operation is happening and the
state and relative phase of the outputs when they begin clocking
again upon completion of the SYNC operation. Between outputs
and after synchronization, this allows for the setting of phase offsets.
The AD9520 differential LVPECL outputs are four groups of
three, sharing a channel divider per triplet. In the case of CMOS,
each LVPECL differential pair can be configured as two single-
ended CMOS outputs. The synchronization conditions apply to
all of the drivers that belong to that channel divider.
Each channel (a divider and its outputs) can be excluded from
any SYNC operation by setting the no sync bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do
not set their outputs static during a SYNC operation, and their
outputs are not synchronized with those of the included channels.
signal is automatically asserted at the beginning and released
upon the completion of a VCO calibration.
Figure 50
Figure 50
Figure 49
), depending on whether
(the VCO divider not
), or one cycle of
AD9520-4
Figure 49