AD9517-0ABCPZ Analog Devices Inc, AD9517-0ABCPZ Datasheet - Page 42
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AD9517-0ABCPZ
Manufacturer Part Number
AD9517-0ABCPZ
Description
12-Output Clock Generator With 2.8GHz VC
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9517-0ABCPZ-RL7.pdf
(80 pages)
Specifications of AD9517-0ABCPZ
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
1:12
Differential - Input:output
Yes/Yes
Frequency - Max
2.95GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LFCSP
Frequency-max
2.95GHz
Function
Clock Generator
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
LFCSP EP
Pin Count
40
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9517-0ABCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD9517-0
Duty Cycle and Duty-Cycle Correction (0, 1)
The duty cycle of the clock signal at the output of a channel is a
result of some or all of the following conditions:
•
•
•
•
The DCC function is enabled by default for each channel divider.
However, the DCC function can be disabled individually for
each channel divider by setting the DCCOFF bit for that channel.
Certain M and N values for a channel divider result in a non-50%
duty cycle. A non-50% duty cycle can also result with an even
division, if M ≠ N. The duty-cycle correction function
automatically corrects non-50% duty cycles at the channel
divider output to 50% duty cycle. Duty-cycle correction
requires the following channel divider conditions:
•
•
When not bypassed or corrected by the DCC function, the duty
cycle of each channel divider output is the numerical value of
(N + 1)/(N + M + 2), expressed as %.
The duty cycle at the output of the channel divider for various
configurations is shown in Table 35 to Table 37.
Table 35. Duty Cycle with VCO Divider; Input Duty Cycle Is 50%
VCO
Divider
Even
Odd = 3
Odd = 5
Even, Odd
Even, Odd
What are the M and N values for the channel?
Is the DCC enabled?
Is the VCO divider used?
What is the CLK input duty cycle? (The internal VCO has
a 50% duty cycle.)
An even division must be set as M = N.
An odd division must be set as M = N + 1.
N + M + 2
1 (divider
bypassed)
1 (divider
bypassed)
1 (divider
bypassed)
Even
Odd
D
X
DCCOFF = 1
50%
33.3%
40%
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
Output Duty Cycle
DCCOFF = 0
50%
50%
50%
50%; requires M = N
50%; requires M = N + 1
Rev. B | Page 42 of 80
Table 36. Duty Cycle with VCO Divider; Input Duty Cycle Is X%
VCO
Divider
Even
Odd = 3
Odd = 5
Even
Odd = 3
Odd = 3
Odd = 5
Odd = 5
Table 37. Channel Divider Output Duty Cycle When the
VCO Divider Is Not Used
Input
Clock
Duty
Cycle
Any
Any
50%
X%
The internal VCO has a duty cycle of 50%. Therefore, when the
VCO is connected directly to the output, the duty cycle is 50%.
If the CLK input is routed directly to the output, the duty cycle of
the output is the same as the CLK input.
N + M + 2
1 (divider
bypassed)
1 (divider
bypassed)
1 (divider
bypassed)
Even
Odd
Even
Odd
Even
Odd
N + M + 2
1
Even
Odd
Odd
D
D
X
X
DCCOFF = 1
50%
33.3%
40%
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
DCCOFF = 1
1 (divider
bypassed)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
Output Duty Cycle
Output Duty Cycle
DCCOFF = 0
50%
(1 + X%)/3
(2 + X%)/5
50%,
requires M = N
50%,
requires M = N + 1
50%,
requires M = N
(3N + 4 + X%)/(6N + 9),
requires M = N + 1
50%,
requires M = N
(5N + 7 + X%)/(10N +
15), requires M = N + 1
DCCOFF = 0
Same as input
duty cycle
50%, requires M = N
50%, requires
M = N + 1
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1