AD9393BBCZ-80 Analog Devices Inc, AD9393BBCZ-80 Datasheet - Page 31

• Manufacturer Part Number: AD9393BBCZ-80
• Description: Pb-free Low Power HDMI Rx
• Manufacturer: Analog Devices Inc

Specifications of AD9393BBCZ-80

• Applications: Video
• Interface: HDMI
• Voltage - Supply: 3.15 V ~ 3.47 V
• Package / Case: 76-CSPBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2-WIRE SERIAL CONTROL PORT
A 2-wire serial interface control interface is provided in the
AD9393.
The 2-wire serial interface is comprised of a clock (SCL) and a
bidirectional data (SDA) ball. The HDMI flat panel interface
acts as a slave for receiving and transmitting data over the serial
interface. When the serial interface is not active, the logic levels
on SCL and SDA are pulled high by external pull-up resistors.
Data received or transmitted on the SDA line must be stable for
the duration of the positive-going SCL pulse. Change data on
SDA only when SCL is low. If SDA changes state while SCL is
high, the serial interface interprets that action as a start or stop
sequence.
There are six components to serial bus operation:
•
•
•
•
•
•
When the serial interface is inactive (SCL and SDA are high),
communications are initiated by sending a start signal. The start
signal is a high-to-low transition on SDA while SCL is high.
This signal alerts all slave devices that a data transfer sequence
is coming.
The first eight bits of data transferred after a start signal
comprise an 7-bit slave address (the first 7 bits) and a single
R/ W bit (the eight bit). The R/ W bit indicates the direction of
the data transfer, read from (1) or write to (0) the slave device. If
the transmitted slave address matches the address of the device,
the AD9393 acknowledges by bringing SDA low on the ninth
SCL pulse. If the addresses do not match, the AD9393 does not
acknowledge.
Table 28. Serial Port Addresses
Bit 7
A
1
6
(MSB)
Start signal
Slave address byte
Base register address byte
Data byte to read or write
Stop signal
Acknowledge (ACK)
Bit 6
A
0
5
SDA
SCL
Bit 5
A
0
t
4
STAH
t
BUFF
Bit 4
A
1
3
Bit 3
A
1
t
2
DHO
Bit 2
A
0
1
t
DAL
Bit 1
A
0
0
Figure 7. Serial Port Read/Write Timing
t
DAH
t
DSU
Bit 0
R/W
Rev. 0 | Page 31 of 40
DATA TRANSFER VIA SERIAL INTERFACE
For each byte of data read or written, the MSB is the first bit of
the sequence.
If the AD9393 does not acknowledge the master device during a
write sequence, the SDA remains high so the master can gener-
ate a stop signal. If the master device does not acknowledge the
AD9393 during a read sequence, the AD9393 interprets this as
the end of data. The SDA remains high, so the master can
generate a stop signal.
To write data to specific control registers of the AD9393, the
8-bit address of the control register of interest must be written
after the slave address has been established. This control register
address is the base address for subsequent write operations. The
base address autoincrements by 1 for each byte of data written
after the data byte intended for the base address. If more bytes
are transferred than there are available addresses, the address
does not increment and remains at its maximum value. Any
base address higher than the maximum value does not produce
an acknowledge signal.
Data are read from the control registers of the AD9393 in a
similar manner. Reading requires two data transfer operations:
•
•
To terminate a read/write sequence to the AD9393, a stop signal
must be sent. A stop signal comprises a low-to-high transition
of SDA while SCL is high.
A repeated start signal occurs when the master device driving
the serial interface generates a start signal without first genera-
ting a stop signal to terminate the current communication.
This is used to change the mode of communication (read,
write) between the slave and master without releasing the
serial interface lines.
The base address must be written with the R/W bit of the
slave address byte low to set up a sequential read operation.
Reading (the R/ W bit of the slave address byte high)
begins at the previously established base address. The
address of the read register autoincrements after each
byte is transferred.
t
STASU
t
STOSU
AD9393