AD9268BCPZ-105 Analog Devices Inc, AD9268BCPZ-105 Datasheet - Page 9

• Manufacturer Part Number: AD9268BCPZ-105
• Description: Dual 16 Bit 105 High SNR ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9268BCPZ-105

• Design Resources: Powering AD9268 with ADP2114 for Increased Efficiency (CN0137)
• Number Of Bits: 16
• Sampling Rate (per Second): 105M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 590mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled,
unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
DATA OUTPUT PARAMETERS
1
2
3
Conversion rate is the clock rate after the divider.
Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17).
Wake-up time is defined as the time required to return to normal operation from power-down mode.
Input Clock Rate
Conversion Rate
CLK Period—Divide-by-1 Mode (t
CLK Pulse Width High (t
Aperture Delay (t
Aperture Uncertainty (Jitter, t
CMOS Mode
LVDS Mode
CMOS Mode Pipeline Delay
LVDS Mode Pipeline Delay (Latency)
Wake-Up Time
Out-of-Range Recovery Time
Data Propagation Delay (t
DCO Propagation Delay (t
(Latency)
DCO to Data Skew (t
Data Propagation Delay (t
DCO Propagation Delay (t
DCO to Data Skew (t
DCS Enabled
DCS Disabled
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode Through Divide-
Channel A/Channel B
by-8 Mode
3
1
A
)
SKEW
SKEW
CH
)
)
)
DCO
PD
DCO
PD
J
)
)
)
)
)
2
CLK
2
)
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
20
10
12.5
3.75
5.95
0.8
2.8
−0.6
2.9
−0.1
AD9268BCPZ-80
Rev. A | Page 9 of 44
Typ
6.25
6.25
1.0
0.07
3.5
3.1
−0.4
3.7
3.9
+0.2
12
12/12.5
500
2
Max
625
80
80
8.75
6.55
4.2
0
4.5
+0.5
Min
20
10
9.5
2.85
4.5
0.8
2.8
−0.6
2.9
−0.1
AD9268BCPZ-105
Typ
4.75
4.75
1.0
0.07
3.5
3.1
−0.4
3.7
3.9
+0.2
12
12/12.5
500
2
Max
6.65
5.0
4.2
0
4.5
+0.5
625
105
105
Min
20
10
8
2.4
3.8
0.8
2.8
−0.6
2.9
−0.1
AD9268BCPZ-125
Typ
4
4
1.0
0.07
3.5
3.1
−0.4
3.7
3.9
+0.2
12
12/12.5
500
2
Max
625
125
125
5.6
4.2
4.2
0
4.5
+0.5
AD9268
Unit
MHz
MSPS
MSPS
ns
ns
ns
ns
ns
ps
rms
ns
ns
ns
ns
ns
ns
Cycles
Cycles
μs
Cycles