AD9255-105EBZ Analog Devices Inc, AD9255-105EBZ Datasheet - Page 9

• Manufacturer Part Number: AD9255-105EBZ
• Description: 14 Bit 105 Msps High SNR 1.8V ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9255-105EBZ

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 105M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 371mW @ 125MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9255
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
1
Timing Diagrams
Refer to
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
Figure 84
for a detailed timing diagram.
D0/1+ TO D12/D13+
D0/1– TO D12/D13–
NOTES
1. DEx DENOTES EVEN BIT.
2. DOx DENOTES ODD BIT.
DCO/DCO+
D0 TO D13
DCO–
CLK+
CLK–
1
VIN
LVDS (DDR) MODE
CMOS MODE
SYNC
Conditions
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
CLK+
Figure 2. LVDS (DDR) and CMOS Output Mode Data Output Timing
N – 1
t
CH
t
DCO
t
t
SSYNC
Figure 3. SYNC Input Timing Requirements
CL
t
PD
N
t
t
A
CLK
DEx
– 12
Rev. A | Page 9 of 44
Dx – 12
t
SKEW
N + 1
DOx
– 12
t
HSYNC
DEx
– 11
Dx – 11
N + 2
DOx
– 11
DEx
– 10
Dx – 10
N + 3
DOx
– 10
DEx
– 9
Dx – 9
Min
2
2
40
2
2
10
10
10
10
N + 4
DOx
– 9
DEx
– 8
Dx – 8
Typ
0.30
0.40
N + 5
DOx
– 8
Max
AD9255
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns