AD9255-105EBZ Analog Devices Inc, AD9255-105EBZ Datasheet - Page 29

• Manufacturer Part Number: AD9255-105EBZ
• Description: 14 Bit 105 Msps High SNR 1.8V ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9255-105EBZ

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 105M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 371mW @ 125MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9255
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 73 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 55). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9255 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 74) and require no external bias.
–0.5
–1.0
–1.5
–2.0
CLK+
2.0
1.5
1.0
0.5
0
–40
Figure 74. Equivalent Clock Input Circuit
–20
4pF
Figure 73. Typical VREF Drift
VREF = 1.0V
0
TEMPERATURE (°C)
AVDD
0.9V
20
CLOCK
CLOCK
INPUT
INPUT
40
Figure 77. Differential PECL Sample Clock (Up to Rated Sample Rate)
50kΩ
60
4pF
CLK–
0.1µF
0.1µF
50kΩ
80
AD95xx
PECL DRIVER
Rev. A | Page 29 of 44
240Ω
Clock Input Options
The AD9255 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of
the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section.
Figure 75 and Figure 76 show two preferred methods for clocking
the AD9255. A low jitter clock source is converted from a single-
ended signal to a differential signal using either an RF
transformer or an RF balun.
The RF balun configuration is recommended for clock frequencies
at 625 MHz and the RF transformer is recommended for clock
frequencies from 10 MHz to 200 MHz. The back-to-back
Schottky diodes across the transformer/balun secondary limit
clock excursions into the AD9255 to approximately 0.8 V p-p
differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9255 while
preserving the fast rise and fall times of the signal that are critical
to low jitter performance.
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 77. The
AD9513/AD9514/AD9515/AD9516/AD9517/AD9518/AD9520/
AD9522
CLOCK
INPUT
240Ω
CLOCK
INPUT
0.1µF
0.1µF
Figure 75. Transformer-Coupled Differential Clock (Up to 200 MHz)
clock drivers offer excellent jitter performance.
100Ω
Figure 76. Balun-Coupled Differential Clock (625 MHz)
50Ω
0.1µF
50Ω
CLK+
CLK–
1nF
1nF
AD9255
100Ω
ADC
ADT1-1WT, 1:1Z
Mini-Circuits
XFMR
0.1µF
®
0.1µF
0.1µF
0.1µF
0.1µF
AD9510/AD9511/AD9512/
SCHOTTKY
SCHOTTKY
HSMS2822
HSMS2822
DIODES:
DIODES:
CLK+
CLK–
AD9255
CLK+
CLK–
AD9255
ADC
AD9255
ADC