AD9229ABCPZRL7-65 Analog Devices Inc, AD9229ABCPZRL7-65 Datasheet - Page 22
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AD9229ABCPZRL7-65
Manufacturer Part Number
AD9229ABCPZRL7-65
Description
Quad 12-Bit 50/65 MSPS, 3V ADC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9229ABCPZRL7-50.pdf
(40 pages)
Specifications of AD9229ABCPZRL7-65
Number Of Bits
12
Sampling Rate (per Second)
65M
Data Interface
Serial
Number Of Converters
4
Power Dissipation (max)
1.47W
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-VFQFN, CSP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9229
If the internal reference of the AD9229 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 44
depicts how the internal reference voltage is affected by loading.
10μF
10μF
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
0.05
+
0
0
SENSE
0.1μF
0.1μF
SENSE
Figure 43. Programmable Reference Configuration
VREF
VREF
R2
R1
VIN+
VIN+
VIN–
VIN–
0.2
Figure 42. Internal Reference Configuration
0.4
Figure 44. VREF Accuracy vs. Load
0.6
SELECT
SELECT
LOGIC
LOGIC
0.8
I
LOAD
1.0
(mA)
CORE
CORE
VREF = 1.0V
ADC
ADC
1.2
0.5V
0.5V
VREF = 0.5V
1.4
REFT
REFB
REFT
REFB
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
1.6
1.8
+
+
10μF
10μF
2.0
Rev. B | Page 22 of 40
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 45 shows the typical drift characteristics of the
internal reference.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. The external
reference is loaded with an equivalent 7 kΩ load. An internal
reference buffer generates the positive and negative full-scale
references, REFT and REFB, for the ADC core. Therefore, the
external reference must be limited to a maximum of 1 V.
Power and Ground Recommendations
When connecting power to the AD9229, it is recommended
that two separate 3.0 V supplies be used: one for analog
(AVDD) and one for digital (DRVDD). If only one supply is
available, it should be routed to the AVDD first and tapped off
and isolated with a ferrite bead or filter choke with decoupling
capacitors proceeding. The user can employ several different
decoupling capacitors to cover both high and low frequencies.
These should be located close to the point of entry at the PC
board level and close to the parts with minimal trace length.
A single PC board ground plane should be sufficient when
using the AD9229. With proper decoupling and smart parti-
tioning of the PC board’s analog, digital, and clock sections,
optimum performance is easily achieved.
–0.02
–0.04
–0.06
–0.08
–0.10
0.10
0.08
0.06
0.04
0.02
0
–40
VREF = 0.5V
–25
Figure 45. Typical VREF Drift
–10
TEMPERATURE (°C)
5
20
VREF = 1.0V
35
50
65
80