AD9212ABCPZ-40 Analog Devices Inc, AD9212ABCPZ-40 Datasheet - Page 25

• Manufacturer Part Number: AD9212ABCPZ-40
• Description: Octal 10 Bit, 40 MSPS Serial LVDS ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9212ABCPZ-40

• Number Of Bits: 10
• Sampling Rate (per Second): 40M
• Data Interface: Serial, SPI™
• Number Of Converters: 8
• Power Dissipation (max): 560mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 60. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Figure 61. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
–100
–200
–300
–400
–500
–100
–200
–300
–400
–500
500
400
300
200
100
500
400
300
200
100
100
–1.5ns
–150ps
–200ps
90
80
70
60
50
40
30
20
10
90
80
70
60
50
40
30
20
10
–1.5ns
0
0
0
0
Greater Than 24 Inches on Standard FR-4
EYE: ALL BITS
EYE: ALL BITS
–1.0ns
–100ps
Less Than 24 Inches on Standard FR-4
–1.0ns
–100ps
–0.5ns
–50ps
–0.5ns
0ns
0ps
0ps
0ns
0.5ns
0.5ns
50ps
ULS: 12071/12071
ULS: 12067/12067
100ps
1.0ns
100ps
1.0ns
150ps
200ps
1.5ns
1.5ns
Rev. D | Page 25 of 56
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
To change the output data format to twos complement, see the
Memory Map section.
Table 8. Digital Output Coding
Code
1023
512
511
0
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 10 bits
times the sample clock rate, with a maximum of 650 Mbps
(10 bits × 65 MSPS = 650 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
a specific application, the PLL can be set up via the SPI to allow
encode rates as low as 5 MSPS. See the Memory Map section for
information about enabling this feature.
Termination On and Trace Lengths Greater Than 24 Inches on Standard FR-4
Figure 62. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω
–100
–200
–300
–400
(VIN + x) − (VIN − x),
Input Span = 2 V p-p (V)
+1.00
0.00
−0.001953
−1.00
400
300
200
100
–150ps
80
70
60
50
40
30
20
10
–1.5ns
0
0
EYE: ALL BITS
–100ps
–1.0ns
–0.5ns
–50ps
0ps
0ns
Digital Output Offset Binary
(D9 ... D0)
11 1111 1111
10 0000 0000
01 1111 1111
00 0000 0000
0.5ns
50ps
ULS: 12072/12072
100ps
1.0ns
AD9212
150ps
1.5ns