AD9212ABCPZ-40 Analog Devices Inc, AD9212ABCPZ-40 Datasheet
AD9212ABCPZ-40
Specifications of AD9212ABCPZ-40
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AD9212ABCPZ-40 Summary of contents
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FEATURES 8 analog-to-digital converters (ADCs) integrated into 1 package 100 mW ADC power per channel at 65 MSPS SNR = 60.8 dB (to Nyquist) ENOB = 9.8 bits SFDR = 80 dBc (to Nyquist) Excellent linearity DNL = ±0.3 LSB ...
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AD9212 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications ...
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SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. 1 Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error ...
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AD9212 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. 1 Parameter SIGNAL-TO-NOISE RATIO (SNR 2.4 MHz IN f ...
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DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. 1 Parameter CLOCK INPUTS (CLK+, CLK−) Logic Compliance 2 Differential Input Voltage ...
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AD9212 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1 p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 4. 1 Temp Parameter 2 CLOCK Maximum Clock Rate Full Minimum Clock ...
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TIMING DIAGRAMS N – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – – 1 VIN ± ...
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AD9212 N – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – FRAME t DATA LSB ...
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ABSOLUTE MAXIMUM RATINGS Table 5. With Parameter Respect To ELECTRICAL AVDD AGND DRVDD DRGND AGND DRGND AVDD DRVDD Digital Outputs DRGND ( − x, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− AGND VIN + x, VIN − x ...
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AD9212 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN + G VIN – G VIN – H VIN + H DRGND DRVDD NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND Table 7. Pin Function Descriptions Pin No. Mnemonic 0 ...
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Pin No. Mnemonic − SCLK/DTP 39 SDIO/ODM 40 CSB 41 PDWN 43 VIN + A 44 VIN − VIN − VIN + B 49 ...
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AD9212 EQUIVALENT CIRCUITS VIN ± x Figure 6. Equivalent Analog Input Circuit 10Ω CLK+ 10kΩ 10kΩ 10Ω CLK– Figure 7. Equivalent Clock Input Circuit 350Ω SDIO/ODM 30kΩ Figure 8. Equivalent SDIO/ODM Input Circuit 1.25V SCLK/DTP OR PDWN Rev ...
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AVDD 70kΩ 1kΩ CSB Figure 12. Equivalent CSB Input Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit VREF Figure 14. Equivalent VREF Circuit Rev Page AD9212 6kΩ ...
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AD9212 TYPICAL PERFORMANCE CHARACTERISTICS 0 –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 15. Single-Tone 32k FFT with f = 2.3 MHz, AD9212- AIN = –0.5dBFS SNR = 61.17dB ENOB = 9.85 ...
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SFDR SNR ENCODE RATE (MSPS) Figure 21. SNR/SFDR vs 10.3 MHz, AD9212-40 SAMPLE IN 90 SFDR SNR ...
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AD9212 100 SFDR 40 30 70dB REFERENCE SNR –60 –50 –40 –30 ANALOG INPUT LEVEL (dBFS) Figure 27. SNR/SFDR vs. Analog Input Level, f 100 SFDR 40 ...
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SFDR 70 65 SNR 100 ANALOG INPUT FREQUENCY (MHz) Figure 33. SNR/SFDR vs AD9212- SFDR SINAD –40 – ...
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AD9212 2.5 2.0 1.5 1.0 0 – – – CODE Figure 39. Input-Referred Noise Histogram, AD9212-65 0 NPR = 51.13dB NOTCH = 18.0MHz NOTCH WIDTH = 3.0MHz –20 –40 ...
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THEORY OF OPERATION The AD9212 architecture consists of a pipelined ADC divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the ...
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AD9212 90 85 SFDR (dBc SNR (dB 0.3 0.6 0.9 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 43. SNR/SFDR vs. Common-Mode Voltage 2.3 MHz, AD9212- SFDR (dBc) ...
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For best dynamic performance, the source impedances driving VIN + x and VIN − x should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer ...
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AD9212 CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9212 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins ...
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Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (f ) due only to aperture jitter (t ) can be calculated by A ...
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AD9212 By asserting the PDWN pin high, the AD9212 is placed into power-down mode. In this state, the ADC typically dissipates 11 mW. During power-down, the LVDS output drivers are placed into a high impedance state. The AD9212 returns to ...
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EYE: ALL BITS 400 300 200 100 0 –100 –200 –300 –400 –500 –1.5ns –1.0ns –0.5ns 0ns 0.5ns –150ps –100ps –50ps 0ps 50ps Figure 60. Data Eye for LVDS ...
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AD9212 Two output clocks are provided to assist in capturing data from the AD9212. The DCO is used to clock the output data and is equal to five times the sample clock (CLK) rate. Data is clocked out of the ...
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When the SPI is used, the DCO phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO+ and DCO− timing, as shown in Figure ...
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AD9212 CSB Pin The CSB pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. This pin is both 1.8 V and 3.3 V ...
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External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift charac- teristics. Figure 66 shows the typical drift characteristics of the internal reference in 1 ...
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AD9212 SERIAL PORT INTERFACE (SPI) The AD9212 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This may provide the user with additional flexibility and ...
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CSB SCLK DON’T CARE R A12 SDIO DON’T CARE Table 15. Serial Timing Definitions Parameter Timing (Minimum, ns CLK ...
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AD9212 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map register table (Table 16) has eight address locations. The memory map is divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), ...
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Table 16. Memory Map Register Addr. (MSB) (Hex) Parameter Name Bit 7 Bit 6 Chip Configuration Registers 00 chip_port_config 0 LSB first off (default) 01 chip_id 02 chip_grade X Child ID [6:4] (identify device ...
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AD9212 Addr. (MSB) (Hex) Parameter Name Bit 7 Bit 6 14 output_mode LVDS ANSI-644 (default LVDS low power, (IEEE 1596.3 similar) 15 output_adjust output_phase user_patt1_lsb user_patt1_msb ...
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APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9212 as a system recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. Power ...
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AD9212 EVALUATION BOARD The AD9212 evaluation board provides all the support cir- cuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially by using a transformer (default AD8334 driver. The ...
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DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9212 Rev. A evaluation board. Power: Connect the switching power supply that is provided with the evaluation ...
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AD9212 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION The following is a brief description of the alternative analog input drive configuration using the AD8334 dual VGA. If this drive option is in use, some components may need to be populated, in which ...
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Figure 74. Evaluation Board Schematic, DUT Analog Inputs Rev Page AD9212 05968-072 ...
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AD9212 Figure 75. Evaluation Board Schematic, DUT Analog Inputs (Continued) Rev Page 05968-073 ...
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R302 DNP 49 VIN+C VIN_C 50 VIN−C VIN_C 51 AVDD_DUT AVDD 52 VIN−D VIN_D 53 R301 VIN_D VIN+D 10kΩ 54 RBIAS 55 VSENSE_DUT SENSE 56 VREF_DUT VREF 57 REFB 58 REFT 59 AVDD_DUT AVDD 60 VIN_E VIN+E 61 VIN−E ...
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AD9212 GND RSET S10 6 VREF Figure 77. Evaluation Board Schematic, ...
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R524 R513 187Ω C512 C511 10µF 0.1µF C510 C509 10µF 0.1µF 49 VCM2 50 VCM1 R504 10kΩ 51 AVDD_5V EN34 R505 10kΩ 52 EN12 53 CLMP12 54 GAIN12 VG12 55 VPS1 AVDD_5V 56 VIN1 57 VIP1 58 LOP1 59 LON1 ...
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AD9212 C610 C609 10µF 0.1µF R605 AVDD_5V 10kΩ AVDD_5V C605 0.1µF R603 274Ω C602 0.018µF 0.1µF C601 AVDD_5V CW GND VG56 Variabl e Gain Circuit (0−1.0V DC) VG56 External Variable Gain Drive Figure 79. Evaluation Board Schematic, Optional DUT Analog ...
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CR702 GREEN R709 0Ω SDO_CHA 0Ω R708 SDI_CHA R707 0Ω SCLK_CHA R706 0Ω CSB1_CHA CR701 2 OPTIONAL GREEN Figure 80. Evaluation Board Schematic, Power Supply Inputs and SPI Interface Circuitry C702 C703 0.1µF 0.1µF PICVCC 1 2 PICVCC GP1 3 ...
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AD9212 Figure 81. Evaluation Board Layout, Primary Side Rev Page ...
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Figure 82. Evaluation Board Layout, Ground Plane Rev Page AD9212 ...
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AD9212 Figure 83. Evaluation Board Layout, Power Plane Rev Page ...
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Figure 84. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page AD9212 ...
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AD9212 Table 17. Evaluation Board Bill of Materials (BOM) Qty per Reference Board Designator Item 1 1 AD9212LFCSP_REVA 2 118 C101, C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C202, C207, C208, C209, C214, C215, C216, ...
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Qty per Reference Item Board Designator 8 8 C503, C514, C520, C526, C603, C614, C620, C626 9 1 C704 10 9 C307, C714, C715, C716, C717, C719, C720, C721, C722 11 16 C540, C541, C544, C545, C548, C549, C552, C553, ...
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AD9212 Qty per Reference Item Board Designator 26 32 L505, L506, L507, L508, L509, L510, L511, L512, L513, L514, L515, L516, L517, L518, L519, L520, L605, L606, L607, L608, L609, L610, L611, L612, L613, L614, L615, L616, L617, L618, L619, ...
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Qty per Reference Item Board Designator 37 8 R161, R162, R163, R164, R208, R225, R241, R259 38 3 R303, R305, R306 39 1 R414 40 1 R404 41 1 R309 42 5 R310, R501, R535, R601, R634 43 1 R308 ...
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AD9212 Qty per Reference Item Board Designator 55 9 T101, T102, T103, T104, T201, T202, T203, T204, T401 56 2 U704, U707 57 2 U501, U601 58 1 U706 59 1 U705 60 1 U301 61 1 U302 62 1 ...
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... INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9212ABCPZ-40 −40°C to +85°C AD9212ABCPZRL7-40 −40°C to +85°C AD9212ABCPZ-65 −40°C to +85°C AD9212ABCPZRL7-65 −40°C to +85°C AD9212-65EBZ RoHS Compliant Part. 9.00 0.60 MAX ...
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AD9212 NOTES ©2006–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05968-0-5/10(D) Rev Page ...