AD9204BCPZ-40 Analog Devices Inc, AD9204BCPZ-40 Datasheet - Page 34

• Manufacturer Part Number: AD9204BCPZ-40
• Description: 10 Bit 40 Msps Dual Low Power ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9204BCPZ-40

• Number Of Bits: 10
• Sampling Rate (per Second): 40M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 97.7mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9204
Addr
(Hex)
0x1C
0x24
0x2A
0x2E
Digital Feature Control
0x10
0
0x10
1
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x100)
Bits[7:3]—Reserved
Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Address 0x100, Bit 0) and the
clock divider sync enable bit (Address 0x100, Bit 1) are high,
Bit 2 allows the clock divider to sync to the first sync pulse it
receives and to ignore the rest. The clock divider sync enable
bit (Address 0x100, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal
is enabled when Bit 1 and Bit 0 are high and the device is
operating in continuous sync mode as long as Bit 2 of the
sync control is low.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions.
Register
Name
USER_PATT2_MSB
MISR_LSB
Features
Output assign
Sync control
(global)
USR2
Bit 7
(MSB)
B15
Open
Open
Open
Open
Enable
OEB
Pin 47
(local)
Bit 6
B14
Open
Open
Open
Open
Open
Bit 5
B13
Open
Open
Open
Open
Open
B12
Open
Open
Open
Open
Open
Bit 4
Rev. 0 | Page 34 of 36
Open
Enable
GCLK
detect
Bit 3
B11
Open
Open
Open
USR2 (Register 0x101)
Bit 7—Enable OEB Pin 47
Normally set high, this bit allows Pin 47 to function as the
output enable. If it is set low, it disables Pin 47.
Bit 3—Enable GCLK Detect
Normally set high, this bit enables a circuit that detects encode
rates below about 5 MSPS. When a low encode rate is detected,
an internal oscillator, GCLK, is enabled, ensuring the proper
operation of several circuits. If set low, the detector is disabled.
Bit 2—Run GCLK
This bit enables the GCLK oscillator. For some applications
with encode rates below 10 MSPS, it may be preferable to set
this bit high to supersede the GCLK detector.
Bit 0—Disable SDIO Pull-Down
This bit can be set high to disable the internal 30 kΩ pull-down
on the SDIO pin, which can be used to limit the loading when
many devices are connected to the SPI bus.
Clock
divider
next sync
only
Run
GCLK
Bit 2
B10
Open
Open
Open
Bit 1
B9
Open
Open
Open
Clock
divider
sync
enable
Open
Bit 0
(LSB)
B8
B0
OR
output
enable
(local)
0 = ADC A
1 = ADC B
(local)
Master
sync
enable
Disable
SDIO
pull-
down
Default
Value
(Hex)
0x00
0x00
0x01
Ch A =
0x00
Ch B =
0x01
0x01
0x88
Comments
User-defined
pattern, 2 MSB
Least significant
byte of MISR; read
only
Disables the OR
pin for the
indexed channel
Assign an ADC to
an output
channel
Enables internal
oscillator for clock
rates < 5 MHz