AD8600APZ Analog Devices Inc, AD8600APZ Datasheet - Page 4

• Manufacturer Part Number: AD8600APZ
• Description: 16 CHANNEL 8-BIT MULT.DAC
• Manufacturer: Analog Devices Inc

Specifications of AD8600APZ

• Rohs Compliant: YES
• Settling Time: 1µs
• Number Of Bits: 8
• Data Interface: Parallel
• Number Of Converters: 16
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): 175mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ELECTRICAL CHARACTERISTICS
Parameter
INTERFACE TIMING
NOTES
1
2
Specifications subject to change without notice.
AD8600
Guaranteed by design not subject to production test.
All logic input signals have maximum rise and fall times of 2 ns.
DATA
ADDR
Clock (EN) Frequency
Clock (EN) High Pulse Width
Clock (EN) LowPulse Width
Data Setup Time
Data Hold Time
Address Setup Time
Address Hold Time
Valid Address to Data Valid
Load Enable Setup Time
Load Enable Hold Time
Read/Write to Clock (EN)
Read/Write to DataBus Hi-Z
Read/Write to DataBus Active
Clock (EN) to Read/Write
Clock (EN) to Chip Select
Chip Select to Clock (EN)
Chip Select to Data Valid
Chip Select to DataBus Hi-Z
Reset Pulse Width
R/W
EN
CS
t
RWZ
t
RWC
t
Figure 2. Write Timing
AS
1, 2
t
CSC
t
DS
t
CH
Figure 4. Write to DAC Register & Voltage Output Settling
OUT
Timing (CS= High, Prevents Input Register Changes)
t
t
RS
LD
EN
DH
AH
t
CL
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CLK
CH
CL
DS
DH
AS
AH
AD
LS
LH
RWC
RWZ
RWD
TWH
TCH
CSC
CSD
CSZ
RS
(@ V
unless otherwise noted)
t
LS
DD1
t
TWH
= V
t
TCH
HIGH-Z
Condition
Data Loading
DD2
t
S1
= V
t
LH
–4–
CC
= +5 V
ADDR
DATA
R/W
EN
CS
5%, V
HIGH -Z
t
EE
t
RWD
CSD
t
RS
= –5 V, V
Figure 3. Readback Timing
t
S1
Min
40
40
40
10
0
0
0
0
30
0
0
30
25
REF
t
AD
= +3.500 V, –40 C T
Typ
Max
12.5
160
120
120
120
150
A
+85 C,
t
CSZ
REV. 0
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns