AD8190ACPZ Analog Devices Inc, AD8190ACPZ Datasheet - Page 12

• Manufacturer Part Number: AD8190ACPZ
• Description: IC,Telecom Switching Circuit,LLCC,56PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD8190ACPZ

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 56-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD8190-9880/PCB - KIT EVAL FOR AD8190 & AD9880
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD8190
THEORY OF OPERATION
INTRODUCTION
The primary function of the AD8190 is to switch one of two
(DVI or HDMI) single-link sources to one output. Each
HDMI/DVI link consists of four differential, high speed
channels and four auxiliary single-ended, low speed control
signals. The high speed channels include a data-word clock and
three transition minimized differential signaling (TMDS) data
channels running at 10× the data-word clock frequency for data
rates up to 1.65 Gbps. The four low speed control signals are
5 V tolerant bidirectional lines that can carry configuration
signals, HDCP encryption, and other information, depending
upon the specific application.
All four high speed TMDS channels are identical; that is, the
pixel clock can be run on any of the four TMDS channels.
Transmit and receive channel compensation is provided for the
high speed channels where the user can (manually) select
among a number of fixed settings.
The AD8190 has I
grammable I
AD8190 is 0b100100X. The least significant bit, represented by
X in the address, is set by tying the I2C_ADDR pin to either
3.3 V (for the value, X = 1) or to 0 V (for X = 0).
INPUT CHANNELS
Each high speed input differential pair terminates to the
3.3 V VTTI power supply through a pair of single-ended 50 Ω
on-chip resistors, as shown in Figure 25. The input terminations
can be optionally disconnected for approximately 100 ms following
a source switch. The user can program which of the eight high
speed input channels employs this feature by selectively setting the
associated RX_PT bits in the input termination pulse register.
Additionally, all the input terminations can be disconnected by
programming the RX_TO bit in the receiver settings register.
The input equalizer can be manually configured to provide two
different levels of high frequency boost: 6 dB or 12 dB. The user
can individually program the equalization level of the eight high
speed input channels by selectively setting the associated RX_EQ
bits in the receive equalizer register. No specific cable length is
suggested for a particular equalization setting because cable
performance varies widely between manufacturers; however, in
general, the equalization of the AD8190 can be set to 12 dB
without degrading the signal integrity, even for short input
cables. At the 12 dB setting, the AD8190 can equalize up to
20 meters of 24 AWG cable at 1080p, over reference cables that
exhibit an insertion loss of −15 dB.
2
C slave addresses. The I
2
C serial programming with two user pro-
2
C slave address of the
Rev. 0 | Page 12 of 24
OUTPUT CHANNELS
Each high speed output differential pair is terminated to the
3.3 V VTTO power supply through two single-ended 50 Ω
on-chip resistors (see Figure 26). This output termination is
user-selectable; all the output terminations can be turned on
or off by programming the TX_PTO bit of the transmitter
settings register.
The AD8190 output has a disable feature that places the outputs
in a tristate mode. This mode is enabled by setting the HS_EN
bit of the high speed device modes register. Larger wire-OR’ e d
arrays can be constructed using the AD8190 in this mode.
The AD8190 requires output termination resistors when the
high speed outputs are enabled. Termination can be internal
and/or external. The internal terminations of the AD8190 are
enabled by setting the TX_PTO bit of the transmitter settings
register (the default upon reset). External terminations can be
provided either by on-board resistors or by the input termination
resistors of an HDMI/DVI receiver. If both internal and external
terminations are provided, set the output current level to 20 mA
by programming the TX_OCL bit of the transmitter settings
register (the default upon reset). If only external terminations
are provided, set the output current level to 10 mA. The high
speed outputs must be disabled if there are no output termination
resistors present in the system.
The output pre-emphasis can be manually configured to provide
one of four different levels of high frequency boost. The specific
boost level is selected by programming the TX_PE bits of the
transmitter settings register. No specific cable length is suggested
for a particular pre-emphasis setting because cable performance
varies widely between manufacturers.
IP_xx
IN_xx
Figure 26. High Speed Output Simplified Schematic
Figure 25. High Speed Input Simplified Schematic
OPx
AVEE
DISABLE
VTTI
50Ω
VTTO
AVEE
50Ω
I
OUT
50Ω
50Ω
CABLE
EQ
ONx