AD7685CCPZRL Analog Devices Inc, AD7685CCPZRL Datasheet - Page 6
![IC,A/D CONVERTER,SINGLE,16-BIT,CMOS,LLCC,10PIN](/photos/6/60/66049/cp-10-9_sml.jpg)
AD7685CCPZRL
Manufacturer Part Number
AD7685CCPZRL
Description
IC,A/D CONVERTER,SINGLE,16-BIT,CMOS,LLCC,10PIN
Manufacturer
Analog Devices Inc
Series
PulSAR®r
Datasheet
1.AD7685BCPZRL7.pdf
(28 pages)
Specifications of AD7685CCPZRL
Design Resources
Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104) Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130)
Number Of Bits
16
Sampling Rate (per Second)
250k
Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
15mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
10-WFDFN, CSP Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-AD7685CBZ - BOARD EVAL FOR AD7685
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD7685
−40°C to +85°C, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
Table 5. VDD = 2.3V to 4.5 V
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
SCK Period (Chain Mode)
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
1
See Figure 3 and Figure 4 for load conditions.
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 2.7 V
VIO Above 2.3 V
Figure 3. Load Circuit for Digital Interface Timing
TO SDO
50pF
C
L
500µA
500µA
1
I
I
OL
OH
1.4V
Rev. B | Page 6 of 28
30% VIO
NOTES
1. 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
t
DELAY
Figure 4. Voltage Levels for Timing
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
2V OR VIO – 0.5V
0.8V OR 0.5V
CONV
ACQ
CYC
CNVH
SCK
SCK
SCKL
SCKH
HSDO
DSDO
EN
DIS
SSDICNV
HSDICNV
SSCKCNV
HSCKCNV
SSDISCK
HSDISCK
DSDOSDI
2
Min
0.7
1.8
5
10
25
29
35
40
12
12
5
30
0
5
8
5
4
1
70% VIO
Typ
t
DELAY
2V OR VIO – 0.5V
0.8V OR 0.5V
Max
3.2
24
30
35
18
22
25
36
2
1
Unit
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns