AD7656BSTZ-1 Analog Devices Inc, AD7656BSTZ-1 Datasheet - Page 22

• Manufacturer Part Number: AD7656BSTZ-1
• Description: 6-CHANNEL 16-BIT SE BIPOLAR I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7656BSTZ-1

• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: Serial, Parallel
• Number Of Converters: 6
• Power Dissipation (max): 143mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7656-1EDZ - BOARD EVAL CONTROL AD7656-1EVAL-AD7656-1CBZ - BOARD EVAL FOR AD7656-1EVAL-AD7656CBZ - BOARD EVAL FOR AD7656
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7656-1/AD7657-1/AD7658-1
The V
processor. The voltage on V
the output logic signals.
The V
decoupling capacitor. These supplies are used for the high voltage
analog input structures on the AD7656-1/AD7657-1/AD7658-1
analog inputs.
DRIVING THE ANALOG INPUTS
Together, the driver amplifier and the analog input circuit used
for the AD7656-1 must settle for a full-scale step input to a 16-bit
level (0.0015%), which is within the specified 550 ns acquisition
time of the AD7656-1. The noise generated by the driver
amplifier needs to be kept as low as possible to preserve the
SNR and transition noise performance of the AD7656-1. In
addition, the driver also needs to have a THD performance
suitable for the AD7656-1.
The
external compensation capacitor of 10 pF. If a dual version of
the AD8021 is required, the
and the
AD7658-1.
INTERFACE OPTIONS
The AD7656-1/AD7657-1/AD7658-1 provide two interface
options: a high speed parallel interface and a high speed serial
interface. The required interface mode is selected via the
SER/ PAR SEL pin. The parallel interface can operate in word
( W /B = 0) or byte ( W /B = 1) mode. When in serial mode, the
AD7656-1/AD7657-1/AD7658-1 can be configured into daisy-
chain mode.
AD8021
DD
DRIVE
AD797
and V
supply is connected to the same supply as the
meets these requirements. The AD8021 needs an
SS
can also be used to drive the AD7656-1/AD7657-1/
signals should be decoupled with a minimum 1 μF
+9.5V TO +16.5V
–9.5V TO –16.5V
DRIVE
AD8022
SUPPLY
2.5V
REF
SUPPLY
ANALOG SUPPLY
controls the voltage value of
VOLTAGE 5V
SIX ANALOG
can be used. The
1µF
1µF
1µF
1µF
INPUTS
+
+
+
+
1µF
+
1
Figure 27. Typical Connection Diagram
See Applications Hints Section
V
AGND
REFCAPA, B, C
AGND
REFIN/OUT
AGND
V
AGND
AD8610
DD
SS
AGND
Rev. 0 | Page 22 of 32
AV
CC
DV
AD7656-1/
AD7657-1/
AD7658-1
CC
DGND
Parallel Interface (SER/ PAR SEL = 0)
The AD7656-1/AD7657-1/AD7658-1 consist of six 16-/14-/
12-bit ADCs, respectively. A simultaneous sample of all six
ADCs can be performed by connecting all three CONVST pins
(CONVST A, CONVST B, and CONVST C) together. The
AD7656-1/AD7657-1/AD7658-1 need to see a CONVST pulse
to initiate a conversion; this should consist of a falling CONVST
edge followed by a rising CONVST edge. The rising edge of
CONVST initiates simultaneous conversions on the selected
ADCs. The AD7656-1/AD7657-1/AD7658-1 each contain an
on-chip oscillator that is used to perform the conversions. The
conversion time, t
indicate the end of a conversion. The falling edge of the BUSY
signal is used to place the track-and-hold amplifier into track mode.
The AD7656-1/AD7657-1/AD7658-1 also allow the six ADCs
to be converted simultaneously in pairs by pulsing the three
CONVST pins independently. CONVST A is used to initiate
simultaneous conversions on V1 and V2, CONVST B is used to
initiate simultaneous conversions on V3 and V4, and CONVST C
is used to initiate simultaneous conversions on V5 and V6. The
conversion results from the simultaneously sampled ADCs are
stored in the output data registers.
Data can be read from the AD7656-1/AD7657-1/AD7658-1 via
the parallel data bus with standard CS and RD signals ( W /B = 0).
To read the data over the parallel bus, SER/ PAR SEL should be
tied low. The CS and RD input signals are internally gated to
enable the conversion result onto the data bus. The data lines
DB0 to DB15 leave their high impedance state when both CS
and RD are logic low.
DV
CC
+
1µF
CONVST A, B, C
V
DRIVE
D0 TO D15
SER/PAR
RANGE
DGND
RESET
BUSY
STBY
W/B
H/S
RD
CS
+
CONV
DIGITAL SUPPLY
VOLTAGE +3V OR +5V
1µF
INTERFACE
PARALLEL
, is 3 μs. The BUSY signal goes low to
V
SCHMITT
TRIGGER
DRIVE
1
µP/µC/DSP