AD7226BRS-REEL Analog Devices Inc, AD7226BRS-REEL Datasheet - Page 5

• Manufacturer Part Number: AD7226BRS-REEL
• Description: Digital To Analog Converter
• Manufacturer: Analog Devices Inc

Specifications of AD7226BRS-REEL

• Rohs Status: RoHS non-compliant
• Settling Time: 4µs
• Number Of Bits: 8
• Data Interface: Parallel
• Number Of Converters: 4
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Power Dissipation (max): -

CIRCUIT INFORMATION
D/A SECTION
The AD7226 contains four identical, 8-bit, voltage mode digital-to-
analog converters. The output voltages from the converters have the
same polarity as the reference voltage allowing single supply opera-
tion. A novel DAC switch pair arrangement on the AD7226 allows a
reference voltage range from 2 V to 12.5 V.
Each DAC consists of a highly stable, thin-film, R-2R ladder
and eight high speed NMOS, single-pole, double-throw
switches. The simplified circuit diagram for one channel is
shown in Figure 1. Note that V
are common to all four DACs.
The input impedance at the V
parallel combination of the four individual DAC reference input
impedances. It is code dependent and can vary from 2 kW to
infinity. The lowest input impedance (i.e., 2 KW) occurs when
all four DACs are loaded with the digital code 01010101.
Therefore, it is important that the reference presents a low
output impedance under changing load conditions. The nodal
capacitance at the reference terminals is also code dependent
and typically varies from 100 pF to 250 pF.
Each V
voltage source with an output voltage of:
where D
and can vary from 0 to 255/256.
The source impedance is the output resistance of the buffer
amplifier.
OP AMP SECTION
Each voltage-mode D/A converter output is buffered by a unity
gain, noninverting CMOS amplifier. This buffer amplifier is
capable of developing 10 V across a 2 kW load and can drive
capacitive loads of 3300 pF. The output stage of this amplifier
consists of a bipolar transistor from the V
load to the V
This output stage is shown in Figure 2.
The NPN transistor supplies the required output current drive
(up to 5 mA). The current load consists of NMOS transistors
which normally act as a constant current sink of 400 mA to V
giving each output a current sink capability of approximately
400 mA if required.
The AD7226 can be operated single or dual supply resulting
in different performance in some parameters from the output
amplifiers.
REV.
AGND
V
REF
V
OUTX
D
OUT
X
Figure 1. D/A Simplified Circuit Diagram
is fractional representation of the digital input code
2R
pin can be considered as a digitally programmable
=
SS
D V
, the negative supply for the output amplifiers.
X
DB0
2R
R
REF
DB5
2R
REF
R
REF
pin of the AD7226 is the
(Pin 4) and AGND (Pin 5)
DB6
2R
SHOWN FOR ALL 1s ON DAC
R
DD
DB7
2R
line and a current
V
OUT
SS
(1)
,
–5–
In single supply operation (V
put approaching AGND (i.e., digital code approaching all 0s)
the current load ceases to act as a current sink and begins to act
as a resistive load of approximately 2 kW to AGND. This occurs
as the NMOS transistors come out of saturation. This means
that, in single supply operation, the sink capability of the ampli-
fiers is reduced when the output voltage is at or near AGND. A
typical plot of the variation of current sink capability with out-
put voltage is shown in Figure 3.
If the full sink capability is required with output voltages at or
near AGND (= 0 V), then V
and thereby maintain the 400 mA current sink as indicated in
Figure 3. Biasing V
in the output amplifier which allows for better zero code error
performance on each output. Also improved is the slew rate and
negative-going settling time of the amplifiers (discussed later).
Each amplifier offset is laser trimmed during manufacture to
eliminate any requirement for offset nulling.
DIGITAL SECTION
The digital inputs of the AD7226 are both TTL and CMOS
(5 V) compatible from V
are static protected MOS gates with typical input currents of
less than 1 nA. Internal input protection is achieved by an
on-chip distributed diode from DGND to each MOS gate. To
minimize power supply currents, it is recommended that the
digital input voltages be driven as close to the supply rails (V
and DGND) as practically possible.
500
400
300
200
100
0
0
Figure 3. Variation of I
V
SS
Figure 2. Amplifier Output Stage
V
SS
= –5V
I/P
= 0
SS
2
below 0 V also gives additional headroom
DD
SS
= 11.4 V to 16.5 V. All logic inputs
SS
4
can be brought below 0 V by 5 V
= 0 V = AGND), with the out-
V
V
V
DD
SS
OUT
(V)
SINK
6
V
DD
with V
400 A
= +15V
O/P
AD7226
8
OUT
10
DD