AD6634BBCZ Analog Devices Inc, AD6634BBCZ Datasheet - Page 37

• Manufacturer Part Number: AD6634BBCZ
• Description: Pb-free Quad Receive Signal Processor
• Manufacturer: Analog Devices Inc
• Series: AD6634r

Specifications of AD6634BBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 196-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Frequency: -
• Gain: -
• Noise Figure: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0x80: Channel Sleep Register
This register contains the SLEEP bit for the channel. When this
bit is high, the channel is placed in a low power state. When this
bit is low, the channel processes data. This bit can also be set by
accessing the SLEEP register at external address 3. When the
External SLEEP register is accessed, all four channels are
accessed simultaneously and the SLEEP bits of the channels
are set appropriately.
0x81: Soft_SYNC Register
This register is used to initiate SYNC events through the
microport. If the Hop bit is written high, the Hop Hold-Off
Counter at address 0x84 is loaded and begins to count down.
When this value reaches 1, the NCO Frequency register used by
the NCO accumulator is loaded with the data from channel
addresses 0x85 and 0x86. When the Start bit is set high, the
Start Hold-Off Counter is loaded with the value at address
0x83 and begins to count down. When this value hits 1, the Sleep
bit in address 0x80 is dropped low and the channel is started.
0x82: Pin_SYNC Register
This register is used to control the functionality of the SYNC
pins. Any of the four SYNC pins can be chosen and monitored
by the channel. The channel can be configured to initiate either
a Start or Hop SYNC event by setting the Hop or Start bit high.
These bits function as enables so that when a SYNC pulse
occurs, either the Start or Hop Hold-Off Counters are activated
in the same manner as with a Soft_SYNC.
0x83: Start Hold-Off Counter
The Start Hold-Off Counter is loaded with the value written to
this address when a Start_Sync is initiated. It can be initiated
by either a Soft_SYNC or Pin_SYNC. The counter begins
REV. 0
Channel
Address
00–7F
80
81
82
83
84
85
86
87
88
89–8F
Register
Coefficient Memory (CMEM)
CHANNEL SLEEP
Soft_Sync Control Register
Pin_SYNC Control Register
Start Hold-Off Counter
NCO Frequency Hold-Off Counter
NCO Frequency Register 0
NCO Frequency Register 1
NCO Phase Offset Register
NCO Control Register
Unused
Table X. Channel Address Memory Map
–37–
Bit
Width
20
1
2
3
16
16
16
16
16
9
decrementing and when it reaches a value of 1, the channel is
brought out of SLEEP and begins processing data. If the channel
is already running, the phase of the filters is adjusted such that
multiple AD6634s can be synchronized. A periodic pulse on the
SYNC pin can be used in this way to adjust the timing of the filters with
the resolution of the ADC sample clock. If this register is written
to a 1, the Start will occur immediately when the SYNC comes
into the channel. If it is written to a 0, no SYNC will occur.
0x84: NCO Frequency Hold-Off Counter
The NCO Frequency Hold-Off Counter is loaded with the value
written to this address when either a Soft_SYNC or Pin_SYNC
comes into the channel. The counter begins counting down so
that when it reaches 1, the NCO frequency word is updated
with the values of addresses 0x85 and 0x86. This is known as a
Hop or Hop_SYNC. If this register is written to a 1, the NCO
Frequency will be updated immediately when the SYNC
comes into the channel. If it is written to a 0, no HOP will
occur. NCO HOPs can be either phase continuous or nonphase
continuous, depending upon the state of Bit 3 of the NCO
control register at channel address 0x88. When this bit is low,
the phase accumulator of the NCO is not cleared but starts to
add the new NCO frequency word to the accumulator as soon as
the SYNC occurs. If this bit is high, the phase accumulator of
the NCO is cleared to 0 and the new word is then accumulated.
0x85: NCO Frequency Register 0
This register represents the 16 LSBs of the NCO Frequency
word. These bits are shadowed and are not updated to the regis-
ter used for the processing until the channel is either brought
out of SLEEP or a Soft_SYNC or Pin_SYNC has been issued.
In the latter two cases, the register is updated when the Frequency
Comments
128 × 20-Bit Memory
0: SLEEP Bit from EXT_ADDRESS 3
1: Hop
0: Start
2: First SYNC Only
1: Hop_En
0: Start_En
Start Hold-Off Value
NCO_FREQ Hold-Off Value
NCO_FREQ[15:0]
NCO_FREQ[31:16]
NCO_PHASE[15:0]
8–7: SYNC Input Select[1:0]
6: WB Input Select B/A
5–4: Input Enable Control
3: Clear Phase Accumulator on HOP
2: Amplitude Dither
1: Phase Dither
0: Bypass (A-Input → I-Path, B → Q)
11: Clock on IEN Transition to Low
10: Clock on IENTransition to High
01: Clock on IEN High
00: Mask on IEN Low
AD6634