AD6634BBCZ Analog Devices Inc, AD6634BBCZ Datasheet - Page 24

• Manufacturer Part Number: AD6634BBCZ
• Description: Pb-free Quad Receive Signal Processor
• Manufacturer: Analog Devices Inc
• Series: AD6634r

Specifications of AD6634BBCZ

• Rf Type: Cellular, CDMA2000, EDGE, GPRS, GSM
• Number Of Mixers: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 196-CSPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Frequency: -
• Gain: -
• Noise Figure: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD6634
Mode 10: Clock on IEN Transition to High
In this mode, data is clocked into the chip only on the first clock
edge after the rising transition of the IEN line. Although data is
latched only on the first valid clock edge, the back end process-
ing (rCIC2, CIC5, and RCF) continues on each available clock
that may be present, similar to Mode 01. The NCO phase accu-
mulator is incremented only once for each new input data sample
and not once for each input clock.
Mode 11: Clock on IEN Transition to Low
In this mode, data is clocked into the chip only on the first clock
edge after the falling transition of the IEN line. Although data is
latched only on the first valid clock edge, the back end process-
ing (rCIC2, CIC5, and RCF) continues one each available
clock that may be present, similar to Mode 01. The NCO phase
accumulator is incremented only once for each new input data
sample and not once for each input clock.
WB Input Select
Bit 6 in this register controls which input port is selected for signal
processing. If this bit is set high, input port B (INB, EXPB, and
IENB) is connected to the selected filter channel. If this bit is
cleared, input port A (INA, EXPA, and IENA) is connected to
the selected filter channel.
Sync Select
Bits 7 and 8 of this register determine which external sync pin is
associated with the selected channel. The AD6634 has four sync
pins named SYNCA, SYNCB, SYNCC, and SYNCD. Any of
these sync pins can be associated with any of the four receiver
channels within the AD6634. Additionally, if only one sync
signal is required for the system, all four receiver channels can
reference the same sync pulse. Bit value 00 is channel A, 01 is
channel B, 10 is channel C, and 11 is channel D.
SECOND ORDER rCIC FILTER
The rCIC2 filter is a second order cascaded resampling integra-
tor comb filter. The resampler is implemented using a unique
technique that does not require the use of a high speed clock,
thus simplifying the design and saving power. The resampler
allows for noninteger relationships between the master clock
and the output data rate, which allows easier implementation of
systems that are either multimode or require a master clock that
is not a multiple of the data rate to be used.
Interpolation up to 512 and decimation up to 4096 is allowed in
the rCIC2. The resampling factor for the rCIC2 (L) is a 9-bit
integer. When combined with the decimation factor M, a 12-bit
number, the total rate change can be any fraction in the form of:
The only constraint is that the ratio L/M must be less than or equal
to one. This implies that the rCIC2 decimates by 1 or more.
Resampling is implemented by apparently increasing the input
sample rate by the factor L, using zero stuffing for the new data
S
OL
rCIC
rCIC
R
R
2
rCIC
rCIC
=
2
ceil
=
2
2
=
≤
L




1
rCIC
log
(
M
L
M
2
2
rCIC
×



M
2
2
2
S
rCIC
rCIC
)
2
2
×
+
input level
floor



_
M
L
rCIC
rCIC
2
2

 ×

–24–



2
samples. Following the resampler is a second order cascaded
integrator comb filter. Filter characteristics are determined only
by the fractional rate change (L/M).
The filter can process signals at the full rate of the input port,
80 MHz. The output rate of this stage is given by the equation:
Both L
rate (L
may be between 1 and 4096. The stage can be bypassed by
setting the decimation to 1/1. The frequency response of the
rCIC2 filter is given by the following equations.
The gain and pass-band droop of the rCIC2 should be calculated
by the equations above, as well as the filter transfer equations that
follow. Excessive pass-band droop can be compensated for in the
RCF stage by peaking the pass band by the inverse of the roll-off.
The scale factor, S
0 and 31. This serves as an attenuator that can reduce the gain
of the rCIC2 in 6 dB increments. For the best dynamic range,
S
attenuation) without creating an overflow condition. This can
be safely accomplished using the equation below, where
input_level is the largest fraction of full scale possible at the input
to the AD6634 (normally 1). The rCIC2 scale factor is always
used whether or not the rCIC2 is bypassed.
Moreover, there are two scale registers (rCIC2_LOUD[4:0]
Bits 4–0 in x92) and (rCIC2_QUIET[4:0] Bits 9–5 in x92) that are
used in conjunction with the computed S
the overall rCIC2 scaling. The S
with the values in each respective scale registers and ExpOff to
determine the scale value that must be placed in the rCIC2 scale
register. This number must be less than 32 or the interpolation
and decimation rates must be adjusted to validate this equation.
The ceil function denotes the next whole integer and the floor func-
tion denotes the previous whole integer. For example, the ceil(4.5)
is 5 while the floor(4.5) is 4.
×
rCIC2
M
scaled_input
scaled_input
rCIC
should be set to the smallest value possible (i.e., lowest
rCIC2
rCIC2
H z
H f
2
( )
( )
–
) may be from 1 to 512 and the decimation (M
and M
L
=
=
rCIC
2
2
S
S
rCIC
2
rCIC
rCIC2
=
=
rCIC2
×
2
2
IN
IN
×
×
floor
1
1
f
SAMP
is a programmable unsigned 5-bit between
L
are unsigned integers. The interpolation
L
×
×
rCIC
rCIC
2
2



2
–
–MOD 7 – Exp + rCIC2,
M
L
2
2
MOD Exp rCIC
=
rCIC
×
rCIC
×
L



 







(
(
rCIC
2
1
2
sin
rCIC2
M
–
+
+
2
rCIC
z
1



1
π
sin



f
–
M
SAMP
L
value must be summed



2
L
z



rCIC
2 32
rCIC



1
rCIC
,




M
rCIC2,
π
2
)
32
rCIC
2
f
,
2
SAMP
)



 

ExpInv
×
f
,
2
which determines
2
ExpInv
f
×
SAMP



f
=









=
0
REV. 0
2
1
rCIC2
)