AD5724RBREZ-REEL7 Analog Devices Inc, AD5724RBREZ-REEL7 Datasheet - Page 6

• Manufacturer Part Number: AD5724RBREZ-REEL7
• Description: Quad 12Bit DAC 0.5 LSB INL + 10ppm Ref
• Manufacturer: Analog Devices Inc

Specifications of AD5724RBREZ-REEL7

• Design Resources: Software Configurable 12-Bit Quad Channel Unipolar/Bipolar Voltage Output Using AD5724R (CN0085)
• Settling Time: 10µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): 310mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5724R/AD5734R/AD5754R
AC PERFORMANCE CHARACTERISTICS
AV
C
Table 3.
Parameter
DYNAMIC PERFORMANCE
1
2
TIMING CHARACTERISTICS
AV
C
Table 4.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
For specified performance, headroom requirement is 0.9 V.
Guaranteed by design and characterization; not production tested.
Guaranteed by characterization; not production tested.
All input signals are specified with t
See Figure 2, Figure 3, and Figure 4.
To accommodate t
Daisy-chain and readback mode.
C
LOAD
LOAD
4
L SDO
5
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Digital Crosstalk
DAC-to-DAC Crosstalk
Digital Feedthrough
Output Noise
Output Noise Spectral Density
5
DD
DD
0.1 Hz to 10 Hz Bandwidth
100 kHz Bandwidth
= capacitive load on SDO output.
= 4.5 V to 16.5 V, AV
= 4.5 V
= 200 pF, all specifications are T
= 200 pF, all specifications T
2
1, 2, 3
1
to 16.5 V, AV
16
, in readback and daisy-chain modes the SCLK cycle time must be increased to 90 ns.
Limit at T
33
13
13
13
13
100
5
0
20
20
20
10
20
2.5
13
40
200
SS
SS
= −4.5 V to −16.5 V or 0 V, GND = 0 V, REFIN = 2.5 V external, DV
= −4.5 V
R
= t
MIN
F
= 5 ns (10% to 90% of DV
MIN
, T
MIN
to T
MAX
1
to −16.5 V or 0 V, GND = 0 V, REFIN= 2.5 V external, DV
to T
MAX
, unless otherwise noted.
MAX
, unless otherwise noted.
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs typ
ns min
μs max
ns min
ns max
ns min
CC
Min
) and timed from a voltage level of 1.2 V.
Rev. C | Page 6 of 32
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (write mode)
Data setup time
Data hold time
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
DAC output settling time
CLR pulse width low
CLR pulse activation time
SYNC rising edge to SCLK falling edge
SCLK rising edge to SDO valid (C
Minimum SYNC high time (readback/daisy-chain mode)
Typ
10
0.6
7.5
3.5
13
35
10
10
15
80
320
Max
12
8.5
5
μs
μs
nV-sec
Unit
μs
V/μs
nV-sec
mV
nV-sec
nV-sec
μV p-p
μV rms
nV/√Hz
Test Conditions/Comments
20 V step to ±0.03 % FSR
10 V step to ±0.03 % FSR
512 LSB step settling (16-bit resolution)
0x8000 DAC code
Measured at 10 kHz, 0x8000 DAC code
CC
L SDO
= 2.7 V to 5.5 V, R
CC
6
= 2.7 V to 5.5 V, R
= 15 pF)
LOAD
LOAD
= 2 kΩ,
= 2 kΩ,