AD5724RBREZ-REEL7 Analog Devices Inc, AD5724RBREZ-REEL7 Datasheet - Page 10

• Manufacturer Part Number: AD5724RBREZ-REEL7
• Description: Quad 12Bit DAC 0.5 LSB INL + 10ppm Ref
• Manufacturer: Analog Devices Inc

Specifications of AD5724RBREZ-REEL7

• Design Resources: Software Configurable 12-Bit Quad Channel Unipolar/Bipolar Voltage Output Using AD5724R (CN0085)
• Settling Time: 10µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): 310mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5724R/AD5734R/AD5754R
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1
2, 6, 12, 13
3
4
5
7
8
9
10
11
14
15
16
17
18, 19
20, 21
22
23
24
25 (EPAD)
Mnemonic
AV
NC
V
V
BIN/2sCOMP
SYNC
SCLK
SDIN
LDAC
CLR
DV
GND
SDO
REFIN/REFOUT
DAC_GND
SIG_GND
V
V
AV
Exposed
Paddle (EPAD)
OUT
OUT
OUT
OUT
SS
DD
CC
A
B
D
C
Description
Negative Analog Supply Pin. Voltage range is from –4.5 V to –16.5 V. This pin can be connected to 0 V if
output ranges are unipolar.
No Connect. Do not connect to these pins.
Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
This pin determines the DAC coding for a bipolar output range. This pin should be hardwired to either DV
or GND. When hardwired to DV
complement. (For unipolar output ranges, coding is always straight binary.)
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred on the falling edge of SCLK. Data is latched on the rising edge of SYNC.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock
speeds up to 30 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
Load DAC, Logic Input. This is used to update the DAC registers and, consequently, the analog output. When
tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high
during the write cycle, the DAC input register is updated, but the output update is held off until the falling
edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC.
The LDAC pin should not be left unconnected.
Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or midscale code (user selectable).
Digital Supply Pin. Voltage range is from 2.7 V to 5.5 V.
Ground Reference Pin.
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is
clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
External Reference Voltage Input and Internal Reference Voltage Output. Reference input range is 2 V to 3 V.
REFIN = 2.5 V for specified performance. REFOUT = 2.5 V ± 2 mV @ 25°C.
Ground reference pins for the four digital-to-analog converters.
Ground reference pins for the four output amplifiers.
Analog Output Voltage of DAC D. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Analog Output Voltage of DAC C. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Positive Analog Supply Pin. Voltage range is from 4.5 V to 16.5 V.
The exposed paddle should be connected to the potential of the AV
electrically unconnected. It is recommended that the paddle be thermally connected to a copper plane for
enhanced thermal performance.
BIN/2sCOMP
NOTES
1. NC = NO CONNECT
2. IT IS RECOMMENDED THAT THE
EXPOSED PAD BE THERMALLY
CONNECTED TO A COPPER PLANE
FOR ENHANCED THERMAL
PERFORMANCE.
V
V
SYNC
SCLK
LDAC
AV
OUT
OUT
SDIN
CLR
NC
NC
NC
SS
A
B
Figure 5. Pin Configuration
10
11
12
1
2
3
4
5
6
7
8
9
Rev. C | Page 10 of 32
CC
(Not to Scale)
AD5724R/
AD5734R/
AD5754R
, input coding is offset binary. When hardwired to GND, input coding is twos
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
13
V
V
AV
SIG_GND
SIG_GND
DAC_GND
REFIN/REFOUT
SDO
GND
DV
DAC_GND
NC
OUT
OUT
DD
CC
C
D
SS
pin or, alternatively, it can be left
CC