AD5557CRU-REEL7 Analog Devices Inc, AD5557CRU-REEL7 Datasheet - Page 13

• Manufacturer Part Number: AD5557CRU-REEL7
• Description: IC,D/A CONVERTER,DUAL,14-BIT,TSSOP,38PIN
• Manufacturer: Analog Devices Inc

Specifications of AD5557CRU-REEL7

• Design Resources: Precision, Unipolar, Inverting Conversion Using AD5547/57 DAC (CN0026) Precision, Unipolar, Noninverting Configuration for the AD5547/57 DAC (CN0027) Precision, Bipolar, Configuration for AD5547/AD5557 DAC (CN0028)
• Settling Time: 500ns
• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 55µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 38-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DIGITAL SECTION
The AD5547/AD5557 have 16-/14-bit parallel inputs. The devices
are double buffered with 16-/14-bit registers. The double buffered
feature allows the simultaneous update of several AD5547s/
AD5557s. For the AD5547, the input register is loaded directly
from a 16-bit controller bus when WR is brought low. The DAC
register is updated with data from the input register when LDAC
is brought high. Updating the DAC register updates the DAC
output with the new data (see
transparent, tie
pin resets the part to zero scale if MSB = 0 and to midscale if
MSB = 1.
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to ground (DGND) and V
As a result, the voltage level of the logic input should not be
greater than the supply voltage.
Amplifier Selection
In addition to offset voltage, the bias current is important in op
amp selection for precision current output DACs. A 30 nA
input bias current in the op amp contributes to 1 LSB in the
full-scale error of the AD5547. The
amps are good candidates for the I-to-V conversion.
Reference Selection
The initial accuracy and rated output of the voltage reference
determine the full-span adjustment. The initial accuracy of the
reference is usually a secondary concern because it can be
trimmed. Figure 24 shows an example of a trimming circuit.
The zero-scale error can also be minimized by standard op amp
nulling techniques.
Figure 18. Equivalent ESD Protection Circuits
WR low and LDAC high. The asynchronous RS
V
DD
DIGITAL
INPUTS
5kΩ
Figure 17
DGND
OP1177
DD
). To make both registers
, as shown in Figure 18.
and
AD8628
op
Rev. B | Page 13 of 20
The voltage reference temperature coefficient (TC) and long-
term drift are primary considerations. For example, a 5 V
reference with a TC of 5 ppm/°C means the output changes by
25 μV/°C. As a result, a reference operating at 55°C contributes
an additional 750 μV full-scale error.
Similarly, the same 5 V reference with a ±50 ppm long-term
drift means the output may change by ±250 μV over time.
Therefore, it is practical to calibrate a system periodically to
maintain its optimum precision.
PCB LAYOUT, POWER SUPPLY BYPASSING, AND
GROUND CONNECTIONS
It is a good practice to employ a compact, minimum lead length,
PCB layout design. The leads to the input should be as short as
possible to minimize IR drop and stray inductance.
The PCB metal traces between V
matched to minimize gain error.
It is also essential to bypass the power supply with quality
capacitors for optimum stability. Supply leads to the device
should be bypassed with 0.01 μF to 0.1 μF disc or chip ceramic
capacitors. Low ESR 1 μF to 10 μF tantalum or electrolytic
capacitors should also be applied at the supply in parallel with
the ceramic capacitor to minimize transient disturbance and
filter out low frequency ripple.
To minimize the digital ground bounce, the AD5547/AD5557
DGND terminal should be joined with the AGND terminal at a
single point. Figure 19 illustrates the basic supply bypassing
configuration and AGND/DGND connection for the
AD5547/AD5557.
5V
+
–
C2
Figure 19. Power Supply Bypassing
1µF
C1
0.1µF
V
AGND
AD5547/AD5557
REF
DD
and R
AD5547/AD5557
FB
DGND
should also be