AD5452YRMZ-REEL7 Analog Devices Inc, AD5452YRMZ-REEL7 Datasheet - Page 7

• Manufacturer Part Number: AD5452YRMZ-REEL7
• Description: IC,D/A CONVERTER,SINGLE,12-BIT,CMOS,TSSOP,8PIN
• Manufacturer: Analog Devices Inc

Specifications of AD5452YRMZ-REEL7

• Design Resources: Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055) Single Supply Low Noise LED Current Source Driver Using a Current Output DAC in the Reverse Mode (CN0139)
• Settling Time: 110ns
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 55µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
TSOT
1
2
3
4
5
6
7
8
N/A
1
N/A = not applicable.
Pin No
MSOP
8
7
6
5
4
3
2
1
N/A
Figure 4. 8-Lead MSOP Pin Configuration
Figure 3. 8-Lead TSOT Pin Configuration
1
SCLK
I
SDIN
OUT
SYNC
GND
LFCSP
8
7
6
5
4
3
2
1
EPAD
V
V
R
REF
DD
FB
1
1
2
3
4
1
2
3
4
AD5452/
AD5453
AD5450/
AD5451/
AD5452/
AD5453
Mnemonic
R
V
V
SYNC
SDIN
SCLK
GND
I
EPAD
OUT
FB
REF
DD
1
8
7
6
5
8
7
6
5
R
V
V
SYNC
I
GND
SCLK
SDIN
REF
DD
FB
OUT
Description
DAC Feedback Resistor. Establish voltage output for the DAC by connecting to external
amplifier output.
DAC Reference Voltage Input.
Positive Power Supply Input. These parts can operate from a supply of 2.5 V to 5.5 V.
Active Low Control Input. This is the frame synchronization signal for the input data. Data is
loaded to the shift register upon the active edge of the following clocks.
Serial Data Input. Data is clocked into the 16-bit input register upon the active edge of the serial
clock input. By default, in power-up mode data is clocked into the shift register upon the falling
edge of SCLK. The control bits allow the user to change the active edge to a rising edge.
Serial Clock Input. By default, data is clocked into the input shift register upon the falling edge
of the serial clock input. Alternatively, by means of the serial control bits, the device can be
configured such that data is clocked into the shift register upon the rising edge of SCLK.
Ground Pin.
DAC Current Output.
Exposed pad must be connected to ground.
1
Rev. E | Page 7 of 32
AD5450/AD5451/AD5452/AD5453
Figure 5. 8-Lead LFCSP Pin Configuration
NOTES
1. THE EXPOSED PAD MUST BE
SCLK
I
OUT
SDIN
GND
CONNECTED TO GROUND.
1
1
2
3
4
(Not to Scale)
AD5453
TOP VIEW
8 R
7 V
6 V
5 SYNC
REF
DD
FB