AD5452YRMZ-REEL7 Analog Devices Inc, AD5452YRMZ-REEL7 Datasheet - Page 18

• Manufacturer Part Number: AD5452YRMZ-REEL7
• Description: IC,D/A CONVERTER,SINGLE,12-BIT,CMOS,TSSOP,8PIN
• Manufacturer: Analog Devices Inc

Specifications of AD5452YRMZ-REEL7

• Design Resources: Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055) Single Supply Low Noise LED Current Source Driver Using a Current Output DAC in the Reverse Mode (CN0139)
• Settling Time: 110ns
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 55µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5450/AD5451/AD5452/AD5453
S
In
in
possible, and p
Because every code change corresponds to a step function
peaking may occur if the op amp has limited gain bandwidth
product (GBP) and there is excessive parasitic capacitance at the
inverting node. This parasitic capacitance introduces a pole into
the open-loop response, which can cause ringing or instability
in the closed-loop applications circuit.
An optional compensation capacitor, C1, can be added in parallel
with R
small a value of C1 can produce ringing
large a value can adversely affect the settling time. C1 should be
found empirically, but 1 pF to 2 pF is generally adequate for th
compensation.
SINGLE-SUPPLY APPLICATIONS
Voltage-Switching Mode
Figure 46 shows these DACs operating in t
mode. The reference voltage, V
the output voltage is available a
configuration, a positive reference voltage results in a positive
output voltage, making single-supply operation possible. The
output from the DAC is voltage at a constant impedance (t
DAC ladder resistance); therefore, an op amp is necessary to
buffer the output voltage. The reference input no longer sees
constant input impedance, but one that varies with code;
therefore, the voltage input should be driven from a low
impedance source.
It is important to note that with this configuration V
to low volta
have the same s
resistance differs, which degrades the integral linearity of the
DAC. Also, V
internal diode turns on, causing the device to exceed the
maximum ratings. In this type of application, the full range of
multiplying capability of the DAC is lost.
tability
verting node of the op amp must be connected as close as
the I-to-V configuration, the I
FB
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
V
IF A1 IS A HIGH SPEED AMPLIFIER.
for stability, as shown in Figure 44 and Figure 45. Too
IN
Figure 46. Single-Supply Voltage-Switching Mode
ges because the switches in the DAC ladde
IN
roper PCB layout techniques must be employed.
ource-drain drive voltage. As a result, t
must not go negative by more than 0.3 V, or an
I
OUT
1
R
FB
GND
V
V
V
IN
t the V
DD
DD
REF
, is applie
OUT
of the DAC and the
R1
REF
at the output, and too
terminal. In this
d to the I
he voltage-switching
R2
OUT
IN
V
r d not
1 pin, and
OUT
heir on
is limited
o
, gain
he
Rev. E | Page 18 of 32
e
P
T
dc r
applied negative reference to
over the output inversion through an inverting amplifier
because of the resistors’ tolerance errors. To generate a negative
reference, the reference can be level-shifted by an op amp such
that the V
ground and −2.5 V, respectively, as shown in Figure 47.
ADDING GAIN
In ap
greater than V
amplifier, or it can b
to consider the effect of the temperature coefficients of the
DAC’s thin film resistors. Simply placing a resistor in series
with the R
coefficients and results in larger gain temperature coefficien
errors. Instead, increase the gain of the circuit by using the
recommended configuration shown in Figure 48. R1, R2, an
R3 should have similar temperature coefficients, but they need
not match the temperature coefficients of the DAC. This
approach is recommended in circuits where gains greater than
are required.
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
ositive Output Voltage
he output voltage polarity is opposite to the V
IF A1 IS A HIGH SPEED AMPLIFIER.
V
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IN
IF A1 IS A HIGH SPEED AMPLIFIER.
+5V
–5V
eference voltages. To achieve a positive voltage output, an
plications in which the output voltage is required to be
V
Figure 47. Positive Output Voltage with Minimum Components
OUT
ADR03
GND
R1
OUT
–2.5V
FB
V
Figure 48. Increasing Gain of Current-Output DAC
IN
resistor causes mismatches in the temperature
and GND pins of the reference become the vir
IN
V
V
REF
V
, gain can be added with an additional external
V
V
DD
REF
DD
DD
V
= +5V
DD
e achieved in a single stage. It is important
GND
GND
R
R
FB
FB
the input of the DAC is preferred
I
I
OUT
OUT
1
1
C1
C1
R3
R2
REF
polarity for
V
GAIN =
R1 =
OUT
R2 + R3
= 0V TO +2.5V
V
R2R3
OUT
R2 + R3
R2
tual
t
d
1