AD1877JRZ-RL Analog Devices Inc, AD1877JRZ-RL Datasheet - Page 9

• Manufacturer Part Number: AD1877JRZ-RL
• Description: IC,+5V 16-BIT STEREO ADC
• Manufacturer: Analog Devices Inc

Specifications of AD1877JRZ-RL

• Number Of Bits: 16
• Sampling Rate (per Second): 45k
• Data Interface: Serial
• Number Of Converters: 2
• Power Dissipation (max): 315mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. A
The ground planes should be tied together at one spot under-
neath the center of the package with an approximately 3 mm
trace. This ground plane technique also minimizes RF transmis-
sion and reception.
Each reference pin (14 and 15) should be bypassed with a 0.1 µF
ceramic chip capacitor in parallel with a 4.7 µF tantalum capaci-
tor. The 0.1 µF chip cap should be placed as close to the pack-
age pin as possible, and the trace to it from the reference pin
should be as short and as wide as possible. Keep this trace away
from any analog traces (Pins 10, 11, 12, 17, 18, 19)! Coupling
between input and reference traces will cause even order har-
monic distortion. If the reference is needed somewhere else on
the printed circuit board, it should be shielded from any signal
dependent traces to prevent distortion.
Wherever possible, minimize the capacitive load on the digital
outputs of the part. This will reduce the digital spike currents
RDEDGE
384/256
DGND1
AGNDL
CAPL1
CAPL2
DV
WCLK
V
LRCK
BCLK
AV
REF
V
DD
S/M
Figure 4. Recommended Ground Plane
IN
DD
1
L
L
10
12
13
14
11
7
1
2
3
4
5
6
8
9
ANALOG GROUND PLANE
DIGITAL GROUND PLANE
22
20
19
18
17
16
15
28
27
26
25
24
23
21
DGND2
CLKIN
TAG
SOUT
DV
RESET
MSBDLY
RLJUST
AGND
V
CAPR2
AGNDR
V
CAPR1
IN
REF
DD
R
R
2
–9–
drawn from the digital supply pins and help keep the IC sub-
strate quiet.
How to Extend SNR
A cost-effective method of improving the dynamic range and
SNR of an analog-to-digital conversion system is to use multiple
AD1877 channels in parallel with a common analog input. This
technique makes use of the fact that the noise in independent
modulator channels is uncorrelated. Thus every doubling of the
number of AD1877 channels used will improve system dynamic
range by 3 dB. The digital outputs from the corresponding deci-
mator channels have to be arithmetically averaged to obtain the
improved results in the correct data format. A microprocessor,
either general-purpose or DSP, can easily perform the averaging
operation.
Shown below in Figure 5 is a circuit for obtaining a 3 dB
improvement in dynamic range by using both channels of a
single AD1877 with a mono input. A stereo implementation
would require using two AD1877s and using the recommended
input structure shown in Figure 2. Note that a single microproces-
sor would likely be able to handle the averaging requirements
for both left and right channels.
DIGITAL INTERFACE
Modes of Operation
The AD1877’s flexible serial output port produces data in
two’s-complement, MSB-first format. The input and output sig-
nals are TTL logic level compatible. Time multiplexed serial
data is output on SOUT (Pin 26), left channel then right chan-
nel, as determined by the left/right clock signal LRCK (Pin 1).
Note that there is no method for forcing the right channel to
precede the left channel. The port is configured by pin selec-
tions. The AD1877 can operate in either master or slave mode,
with the data in right-justified, I
controlled or left-justified positions.
The various mode options are pin-programmed with the Slave/
Master Pin (7), the Right/Left Justify Pin (21), and the MSB
Delay Pin (22). The function of these pins is summarized as
follows:
CHANNEL
SINGLE
Figure 5. Increasing Dynamic Range By Using Two
AD1877 Channels
INPUT
RECOMMENDED
INPUT BUFFER
AD1877
AD1877
V
V
IN
IN
2
R
L
S-compatible, Word Clock
AVERAGER
DIGITAL
AD1877
SINGLE
CHANNEL
OUTPUT