AD1877JR Analog Devices Inc, AD1877JR Datasheet
AD1877JR
Specifications of AD1877JR
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AD1877JR Summary of contents
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FEATURES Single 5 V Power Supply Single-Ended Dual-Channel Analog Inputs 92 dB (Typ) Dynamic Range 90 dB (Typ) S/(THD+N) 0.006 dB Decimator Passband Ripple Fourth-Order, 64-Times Oversampling Three-Stage, Linear-Phase Decimator 256 F or 384 F Input Clock S S ...
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AD1877–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages Ambient Temperature ) [256 × F Input Clock (F ] CLKIN S Input Signal Measurement Bandwidth Load Capacitance on Digital Outputs Input Voltage Input Voltage ...
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DIGITAL I/O Input Voltage Input Voltage Input Leakage ( Input Leakage ( Output Voltage ...
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... AD1877 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Package Model Temperature Description AD1877JR 0°C to 70°C SOIC Min 0 –60 Min ...
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PIN FUNCTION DESCRIPTIONS Input/ Pin Pin Output Name Description 1 I/O LRCK Left/Right Clock 2 I/O WCLK Word Clock 3 I/O BCLK Bit Clock Digital Supply DGND1 Digital Ground 6 I ...
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AD1877 ( ) Continued from Page 1 The flexible serial output port produces data in twos-comple- ment, MSB-first format. The input and output signals are TTL compatible. The port is configured by pin selections. Each 16-bit output word of a ...
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Sample Delay The sample delay or “group delay” of the AD1877 is dominated by the processing time of the digital decimation filter. FIR fil- ters convolve a vector representing time samples of the input with an equal-sized vector of coefficients. ...
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AD1877 The AD1877 also features a power-down mode enabled by the active LO RESET Pin 23 (i.e., the AD1877 is in powerdown mode while RESET is held LO). The power savings are speci- fied in the ‘’Specifications’’ section ...
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The ground planes should be tied together at one spot under- neath the center of the package with an approximately 3 mm trace. This ground plane technique also minimizes RF transmis- sion and reception. 1 LRCK WCLK 2 BCLK 3 ...
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AD1877 MSBDLY S/M RLJUST WCLK Output Input Output Output Output Output Output Output Serial Port Data ...
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Two modes deserve special discussion. The first special mode, “Slave Mode, Data Position Controlled by WCLK Input” (S/M = HI, RLJUST = HI, MSBDLY = LO), shown in Figure 8, is the only mode in which WCLK is an input. ...
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AD1877–Typical Performance Characteristic Curves 100 120 140 FREQUENCY – kHz TPC 1. 1 kHz Tone at –0.5 dBFS (16k-Point FFT) 0 –20 –40 –60 –80 –100 –120 ...
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LRCK INPUT BCLK RDEDGE = INPUT BCLK RDEDGE = HI PREVIOUS DATA SOUT ZEROS MSB-14 LSB OUTPUT WCLK OUTPUT LEFT TAG TAG MSB LSB OUTPUT Figure 7. Serial Data Output Timing: Slave Mode, Right-Justified with ...
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AD1877 LRCK INPUT BCLK RDEDGE = LO INPUT BCLK RDEDGE = HI LEFT DATA SOUT ZEROS MSB OUTPUT MSB-1 WCLK OUTPUT LEFT TAG TAG MSB LSB OUTPUT Figure 9. Serial Data Output Timing: Slave Mode, Left-Justified ...
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LRCK OUTPUT BCLK RDEDGE = LO OUTPUT BCLK RDEDGE = HI PREVIOUS DATA SOUT MSB-14 LSB OUTPUT WCLK OUTPUT LEFT TAG TAG MSB LSB OUTPUT Figure 12. Serial Data Output Timing. Master Mode, Right-Justified with MSB Delay, ...
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AD1877 LRCK INPUT BCLK RDEDGE = LO INPUT BCLK RDEDGE = HI PREVIOUS DATA SOUT LSB MSB OUTPUT MSB-14 WCLK OUTPUT TAG MSB OUTPUT Figure 15. Serial Data Output Timing: Slave Mode, Left-Justified with No MSB Delay, ...
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BCLK INPUT RDEDGE = LO BCLK OUTPUT RDEDGE = HI LRCK INPUT WCLK INPUT DATA & TAG OUTPUTS t CPWH CLKIN INPUT RESET INPUT REV BPWL XMIT SAMPLE XMIT SAMPLE t BPWH t SETLRBS t SETWBS t t ...
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AD1877 PIN 1 0.0118 (0.30) 0.0040 (0.10) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). R-28 (S-Suffix) 28-Lead Wide-Body SO SOL- 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00 0.1043 (2.65) 0.7125 (18.10) 0.0926 (2.35) 0.6969 ...
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