A8515GLPTR-T Allegro Microsystems Inc, A8515GLPTR-T Datasheet - Page 14

• Manufacturer Part Number: A8515GLPTR-T
• Description: Backlight Driver For Medium Size LCDs
• Manufacturer: Allegro Microsystems Inc

Specifications of A8515GLPTR-T

• Constant Current: *
• Constant Voltage: *
• Internal Driver: *
• Type - Primary: *
• Type - Secondary: *
• Mounting Type: Surface Mount
• Topology: *
• Number Of Outputs: *
• Frequency: *
• Voltage - Supply: *
• Voltage - Output: *
• Package / Case: 16-TSSOP Exposed Pad, 16-eTSSOP, 16-HTSSOP
• Operating Temperature: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A8515
The basic requirement of the sync signal is 150 ns minimum on-
time and 150 ns minimum off time, as indicated by the specifica-
tions for t
for a synchronization clock into the A8515 at 2.2 MHz. Thus any
pulse with a duty cycle of 33% to 66% at 2.2 MHz can be used to
synchronize the IC. The rise and fall edges should be about 10 ns.
The SYNC pulse duty cycle ranges for selected switching fre-
quencies are:
If during operation a sync clock is lost, the IC will revert to the
preset switching frequency that is set by the resistor R
ing this period the IC will stop switching for a maximum period
of about 7 μs to allow the sync detection circuitry to switch
over to the externally preset switching frequency. If the clock is
held low for more than 7 μs, the A8515 will shut down. In this
shutdown mode the IC will stop switching, the input discon-
nect switch is open, and the LEDs will stop sinking current. To
shutdown the IC into low power mode, the user needs to disable
the IC using the PWM pin, by keeping the pin low for a period
of 65 ms. If the FSET pin is released at any time after 5 μs, the
A8515 will proceed to soft start.
Figure 9. SYNC pulse on and off time requirements.
SYNC Pulse Frequency
PWSYNCON
(MHz)
0.800
0.600
2.2
2
1
t
PWSYNCON
150 ns
and t
T = 454 ns
PWSYNCOFF
154 ns
t
PWSYNCOFF
150 ns
. Figure 9 shows the timing
Duty Cycle Range
33 to 66
30 to 70
15 to 85
12 to 88
9 to 91
(%)
Wide Input Voltage Range, High Efficiency
FSET
. Dur-
LED current setting and LED dimming
The maximum LED current can be up to 120 mA per channel,
and is set through the ISET pin. To set the ILED current, connect
a resistor, R
lowing formula:
where I
rent through the LEDs, referred to as the 100% current. Standard
R
PWM dimming
The LED current can be reduced from the 100% current level
by PWM dimming using the PWM pin. When the PWM pin
is pulled high, the A8515 turns on and all enabled LEDs sink
100% current. When PWM is pulled low, the boost converter
and LED sinks are turned off. The compensation (COMP) pin is
floated, and critical internal circuits are kept active. The typical
PWM dimming frequencies fall between 200 Hz and 1 kHz. Fig-
ures 11A to 11D provide examples of PWM switching behavior.
Another important feature of the A8515 is the PWM signal to
LED current delay. This delay is typically less than 500 ns, which
allows greater accuracy at low PWM dimming duty cycles, as
shown in figure 10.
Figure 10. Percentage Error of the LED current versus PWM duty cycle.
ISET
values, at gain equals 980, are as follows:
Standard Closest R
LED
10
8
6
4
2
0
0.1
Resistor Value
ISET
is in A and R
Fault Tolerant LED Driver
(kΩ)
8.25
9.76
12.1
15.0
, between this pin and GND, according to the fol-
R
ISET
ISET
PWM Duty Cycle, D (%)
ISET
1
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
is in Ω. This sets the maximum cur-
= 980 / I
LED current per LED, I
LED
10
(mA)
120
100
80
65
100
LED
(1)
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