A3981KLPTR-T Allegro Microsystems Inc, A3981KLPTR-T Datasheet - Page 8

• Manufacturer Part Number: A3981KLPTR-T
• Description: AUTOMOTIVE PROGRAMMABLE STEPPER DRVR
• Manufacturer: Allegro Microsystems Inc

Specifications of A3981KLPTR-T

• Applications: Stepper Motor Driver, 2 Phase
• Number Of Outputs: 1
• Voltage - Load: 7 V ~ 28 V
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width) Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A3981
The A3981 is an automotive stepper motor driver suitable for
high temperature applications such as headlamp bending and
leveling, throttle control, and gas recirculation control. It is also
suitable for other low current stepper applications such as air con-
ditioning and venting. It provides a highly flexible microstepping
motor driver that can be configured via the SPI-compatible serial
interface. It can be controlled with simple Step and Direction
inputs, for high speed stepping applications, or directly through
the serial interface by writing a step change value.
The two DMOS full bridges are capable of driving bipolar step-
per motors in full-, half-, quarter-, eighth- and sixteenth-step
modes, at up to 28 V and ±750 mA. The current in each phase
of the stepper motor is regulated by a peak detect PWM cur-
rent control scheme that can be programmed to operate in fixed
off-time or fixed frequency. Several decay modes can be selected
to reduce audible motor noise and increase step accuracy. In
addition the phase current tables, which default to a sinusoidal
current profile, can be programmed via the serial interface to
create unique microstep current profiles to further improve motor
performance for specific applications.
The outputs are protected from short circuits, and features for
open load and stalled rotor detection are included. Chip level pro-
tection includes hot and cold thermal warning, overtemperature
shutdown, and overvoltage and undervoltage lockout.
Pin Functions
VBBA, VBBB Main motor supply and chip supply for internal
regulators and charge pump. VBBA and VBBB should be con-
nected together and each decoupled to ground with a low ESR
electrolytic capacitor and a good ceramic capacitor.
Note: Any reference to “VBB” in this specification is defined as
applying to both VBBA and VBBB.
CP1, CP2 Pump capacitor connection for charge pump. Connect
a 100 nF (50 V) ceramic capacitor between CP1 and CP2.
VCP Above-supply voltage for high-side drive. A 100 nF (16 V)
ceramic capacitor should be connected between VCP and VBB to
provide the pump storage reservoir.
VDD Logic supply. Compatible with 3.3 V and 5 V logic. Should
be decoupled to ground with a 100 nF (10 V) ceramic capacitor.
VREG Regulated supply for bridge gate drive. Should be decou-
pled to ground with a 470 nF (10 V) ceramic capacitor.
Functional Description
Automotive, Programmable Stepper Driver
AGND Analog reference ground. Quiet return for measurement
and input references. Connect to PGND (see Layout section).
PGND Digital and power ground. Connect to supply ground and
AGND (see Layout section).
OAP, OAM Motor connection for phase A. Positive motor phase
current direction is defined as flowing from OAM to OAP.
OBP, OBM Motor connection for phase B. Positive motor phase
current direction is defined as flowing from OBM to OBP.
SENSA Phase A current sense. Connect sense resistor between
SENSA and PGND.
SENSB Phase B current sense. Connect sense resistor between
SENSB and PGND.
REF Reference input to set absolute maximum current level for
both phases. Defaults to internal reference when tied to VDD.
STEP Step logic input. Motor advances on rising edge. Filtered
input with hysteresis.
DIR Direction logic input. Direction changes on the next STEP
rising edge. When high, the Phase Angle Number is increased
on the rising edge of STEP. Has no effect when using the serial
interface. Filtered input with hysteresis.
MS0 Microstep resolution select input.
MS1 Microstep resolution select input.
RESETn Resets faults when pulsed low. Forces low-power shut-
down (sleep) when held low for more than the Reset Shutdown
Width, t
ENABLE Controls activity of bridge outputs. When held low,
deactivates the outputs, that is, turns off all output bridge FETs.
Internal logic continues to follow input commands.
SDI Serial data input. 16-bit serial word input MSB first.
SDO Serial data output. High impedance when STRn is high. Out-
puts bit 15 of the diagnostic registers (Fault Register 0 and Fault
Register 1), the Fault Register flag, as soon as STRn goes low.
SCK Serial interface clock. Data is latched in from SDI on the
rising edge of the SCK clock signal. There must be 16 rising
edges per write and SCK must be held high when STRn changes.
STRn Serial data strobe and serial access enable. When STRn
is high any activity on SCK or SDI is ignored, and SDO is high
RSD
. Can be pulled to VBB with 30 kΩ resistor.
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
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