A3981KLPTR-T Allegro Microsystems Inc, A3981KLPTR-T Datasheet - Page 16

• Manufacturer Part Number: A3981KLPTR-T
• Description: AUTOMOTIVE PROGRAMMABLE STEPPER DRVR
• Manufacturer: Allegro Microsystems Inc

Specifications of A3981KLPTR-T

• Applications: Stepper Motor Driver, 2 Phase
• Number Of Outputs: 1
• Voltage - Load: 7 V ~ 28 V
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP (0.173", 4.40mm Width) Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A3981
An optional simple odd parity scheme is included to provide
some measure of error checking, if required. Each 6-bit value
can be supplemented with an additional parity bit, PTP, to ensure
an odd number of 1s in the transmission. This is checked by the
A3981 and if a the number of 1s in the value plus parity bit is not
odd, the FF bit will be set and the SDO pin will go high the next
time STRn is taken low, indicating a parity error. That data will
still be written to the next phase table value address; it is incum-
bent upon the external controller to take action, if required.
If the write sequence is broken (by a reset, by writing to another
register, or by a data transfer error) before the sequence has been
completed, then the phase table value address will be reset to
PT(0). If it is required to load the table, then the entire 16-value
sequence must be sent.
After loading, although the phase current table is volatile, a reset
using a low pulse on the RESETn pin does not corrupt the table.
The table is only reset to default values on a power-on reset.
Automotive, Programmable Stepper Driver
Diagnostic Registers
The diagnostic registers comprise two read-only fault data regis-
ters. Access is described in the section Reading from Diagnostic
Registers, above.
The diagnostic registers contain fault flags for each fault condi-
tion and are reset to all 0s on the completion of each serial access.
They are also reset to all 0s each time the RESETn input is low
for longer than the Reset Pulse Width, t
all 1s at power-up or after a power-on reset. This indicates to the
external controller that a power-on reset has taken place and all
registers have been reset. Note that a power-on reset only occurs
when the V
Power-on reset function is not affected by the state of the motor
supply or V
The first bit in both registers is the Fault Register flag, FF. This
is high if any bits in FAULT0 are set, or if a serial write error or
parity error has occurred.
DD
REG
supply rises above its undervoltage threshold.
.
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
RST
. FAULT0 is set to
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