A3941KLPTR-T Allegro Microsystems Inc, A3941KLPTR-T Datasheet - Page 15

• Manufacturer Part Number: A3941KLPTR-T
• Description: IC,Motor Controller,TSSOP,28PIN
• Manufacturer: Allegro Microsystems Inc

Specifications of A3941KLPTR-T

• Configuration: H Bridge
• Input Type: PWM
• Delay Time: 90ns
• Number Of Configurations: 1
• Number Of Outputs: 4
• Voltage - Supply: 5.5 V ~ 50 V
• Operating Temperature: -40°C ~ 150°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP Exposed Pad, 28-eTSSOP, 28-HTSSOP
• Number Of Drivers: 4
• Driver Configuration: Non-Inverting
• Driver Type: High and Low Side
• Rise Time: 35ns
• Fall Time: 20ns
• Propagation Delay Time: 150ns
• Operating Supply Voltage (max): 50V
• Operating Supply Voltage (min): 5.5V
• Operating Temp Range: -40C to 150C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: TSSOP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Peak: -
• High Side Voltage - Max (bootstrap): -
• Lead Free Status / Rohs Status: Compliant
• Other names: 620-1236-2

A3941
For R
nal value of t
where R
of R
The I
The maximum dead time, 6 μs typical, can be set by connecting
the RDEAD pin directly to the V5 pin.
The choice of power FET and external series gate resistance
determine the selection of the dead-time resistor, R
dead time should be long enough to ensure that one FET in a
phase has stopped conducting before the complementary FET
starts conducting. This should also take into account the tolerance
and variation of the FET gate capacitance, the series gate resis-
tance, and the on-resistance of the A3941 internal drives.
Dead time will be present only if the on-command for one FET
occurs within t
FET. In the case where one side of a phase drive is permanently
off, for example when using diode rectification with slow decay,
then the dead time will not occur. In this case the gate drive will
turn on within the specified propagation delay after the corre-
sponding phase input goes high. (Refer to the Gate Drive Timing
diagrams.)
Fault Blank Time
To avoid false short fault detection, the output from the V
monitor for any FET is ignored when that FET is off and for a
period of time after it is turned on. This period of time is the fault
blank time. Its length is the dead time, t
period of time that compensates for the delay in the V
tors. This additional delay is typically 300 to 600 ns.
Braking
The A3941 can be used to perform dynamic braking either by
forcing all low-side FETs on and all high-side FETs off (SR=1,
PWMH=0, and PWML=1) or conversely by forcing all low-
side FETs off and all high-side FETs on (SR=1, PWMH=1, and
DEAD
DEAD
DEAD
DEAD
t
DEAD
between 6 and 60 kΩ, which are shown in figure 3.
current can be estimated by:
values between 3 kΩ and 240 kΩ, at 25°C the nomi-
DEAD
is in kΩ. Greatest accuracy is obtained for values
DEAD
(nom)
in ns can be approximated by:
after the off-command for its complementary
=
I
50 +
DEAD
=
1.2 + (200 / R
R
DEAD
1.2
DEAD
7200
.
, plus an additional
DEAD
DEAD
Automotive Full Bridge MOSFET Driver
)
DS
. The
moni-
DS
,
(1)
(2)
PWML=0). This effectively short-circuits the back EMF of the
motor, creating a breaking torque.
During braking, the load current can be approximated by:
where V
resistance of the phase winding.
Care must be taken during braking to ensure that maximum rat-
ings of the power FETs are not exceeded. Dynamic braking is
equivalent to slow decay with synchronous rectification.
Bootstrap Capacitor Selection
The bootstrap capacitors, C
ensure proper operation of the A3941. If the capacitances are too
high, time will be wasted charging the capacitor, resulting in a
limit on the maximum duty cycle and the PWM frequency. If the
capacitances are too low, there can be a large voltage drop at the
time the charge is transferred from C
to charge sharing.
To keep this voltage drop small, the charge in the bootstrap
capacitor, Q
by the gate of the FET, Q
value, and the following formula can be used to calculate the
value for C
therefore:
where V
The voltage drop across the bootstrap capacitor as the FET is
being turned on, ∆V , can be approximated by:
So, for a factor of 20, ∆V would be approximately 5% of V
The maximum voltage across the bootstrap capacitor under
normal operating conditions is V
circumstances the voltage may transiently reach 18 V, the clamp
Q
BEMF
BOOT
BOOT
BOOT
BOOT
is the voltage across the bootstrap capacitor.
is the voltage generated by the motor and R
=
:
, should be much larger than the charge required
C
BOOT
C
BOOT
I
∆V ≈
BRAKE
× V
GATE
=
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
BOOTx
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
BOOT
Q
. A factor of 20 is a reasonable
C
Q
GATE
=
BOOT
V
GATE
REG
, must be correctly selected to
BOOT
V
= Q
BEMF
R
× 20
(max). However, in some
BOOTx
L
GATE
.
to the FET gate, due
× 20 ,
,
,
L
BOOT
is the
(3)
(4)
(5)
15
.