74ALVCH16825DGG:11 NXP Semiconductors, 74ALVCH16825DGG:11 Datasheet - Page 2

• Manufacturer Part Number: 74ALVCH16825DGG:11
• Description: 74ALVCH16825DGG/TSSOP56/REEL13
• Manufacturer: NXP Semiconductors
• Series: 74ALVCHr

Specifications of 74ALVCH16825DGG:11

• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 2
• Number Of Bits Per Element: 9
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 1.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Logic Family: ALVC
• Number Of Channels Per Chip: 18
• Polarity: Non-Inverting
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 24 mA
• Low Level Output Current: 24 mA
• Minimum Operating Temperature: - 40 C
• Number Of Lines (input / Output): 18 / 18
• Output Type: 3-State
• Propagation Delay Time: 2.1 ns at 1.2 V, 2 ns at 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ALVCH16825DG-T; 74ALVCH16825DG-T; 935259050118

1. C
Philips Semiconductors
FEATURES
DESCRIPTION
The 74ALVCH16825 is an 18–bit non-inverting buffer/driver with
3-State outputs for bus-oriented applications.
The 74ALVCH16825 consists of two 9-bit sections with separate
output enable signals. For either 9-bit buffer section, the two output
enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be
LOW for corresponding D outputs to be active. If either output
enable input is HIGH, the outputs of that 9-buffer section are in the
high impedance state.
The 74ALVCH16825 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING INFORMATION
56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II
1998 Jul 27
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive
MULTIBYTE
Low inductance multiple V
and ground bounce
All data inputs have bus hold
Output drive capability 50 transmission lines @ 85 C
18-bit buffer/driver (3-State)
t
C
C
C
PHL
P
f
SYMBOL
o
I
PD
PD
PD
D
= output frequency in MHz; V
= C
/t
PLH
is used to determine the dynamic power dissipation (P
PD
amb
TM
V
= 25 C; t
CC
24 mA at 3.0 V
flow-through standard pin-out architecture
Propagation delay
CP to Qn
Input capacitance
Power dissipation capacitance per latch
Power dissi ation ca acitance er latch
2
f
i
PACKAGES
+ S (C
r
= t
CC
f
L
and GND pins for minimum noise
2.5ns
PARAMETER
V
CC
CC
= supply voltage in V; S (C
2
f
o
) where: f
i
= input frequency in MHz; C
D
TEMPERATURE
–40 C to +85 C
in W):
L
V
V
V
V
CC
CC
I
I
RANGE
= GND to V
= GND to V
V
CC
= 2.5V, C
= 3.3V, C
2
2
PIN CONFIGURATION
f
o
) = sum of outputs.
L
L
CC
CC
= 30pF
= 50pF
1
1
L
CONDITIONS
74ALVCH16825 DGG
= output load capacitance in pF;
OUTSIDE NORTH
AMERICA
1OE1
2OE1
GND
GND
GND
GND
GND
GND
V
V
1Y
1Y
1Y
1Y
1Y
1Y
1Y
1Y
1Y
2Y
2Y
2Y
2Y
2Y
2Y
2Y
2Y
2Y
CC
CC
1
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
Output disabled
Output enabled
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
11
1
2
3
4
5
6
7
8
9
NORTH AMERICA
ACH16825 DGG
74ALVCH16825
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
TYPICAL
SH00139
1A
1A
GND
1A
1A
V
1A
1A
1A
GND
1A
1A
GND
GND
2A
2A
GND
2A
2A
2A
V
2A
2A
GND
2A
2A
Product specification
2OE2
1OE2
CC
CC
2.0
2.0
4.0
19
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
3
853-2097 19785
DRAWING
SOT364-1
NUMBER
UNIT
pF
pF
ns
F