74ALVCH16823DGG:11 NXP Semiconductors, 74ALVCH16823DGG:11 Datasheet - Page 8

• Manufacturer Part Number: 74ALVCH16823DGG:11
• Description: 74ALVCH16823DGG/TSSOP56/TUBE-B
• Manufacturer: NXP Semiconductors
• Series: 74ALVCHr
• Type: D-Type Busr

Specifications of 74ALVCH16823DGG:11

• Function: Master Reset
• Output Type: Tri-State Non Inverted
• Number Of Elements: 2
• Number Of Bits Per Element: 9
• Frequency - Clock: 300MHz
• Delay Time - Propagation: 2.8ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ALVCH16823DG; 74ALVCH16823DG; 935259030112

Philips Semiconductors
AC WAVEFORMS FOR V
V
V
V
V
V
output load.
V
AC WAVEFORMS FOR V
V
V
V
V
V
output load.
V
1998 Jul 29
Waveform 3. Data Setup and Hold Times for the D
Waveform 1. Clock (nCP) to Output (nQn) Propagation Delays,
I
I
M
X
Y
OL
M
X
Y
OL
nMR
nCP
CC
CC
nCP
nQn
nQn
= V
= 2.7V
18-bit D-type flip-flop (3-State)
Output propagation Delay and MR to Clock Recovery Time
= V
= V
= V
= V
Clock Pulse Width, and Maximum Clock Pulse Frequency
= 0.5 V
= 1.5 V
and V
and V
< 2.3V RANGE
CC
= 2.7V RANGE
OL
OH
OL
OH
Waveform 2. Master Reset (MR) Pulse WIdth, MR to
nCE, nD
NOTE: The data set-up and hold times for D
nQ
+ 0.15V
+ 0.3V
–0.15V
–0.3V
OH
OH
CC
nCP INPUT
n
OUTPUT
V
n
are the typical output voltage drop that occur with the
are the typical output voltage drop that occur with the
t
M
PHL
INPUT
t
w
GND
GND
V
V
OH
OL
V
V
I
I
V
1/f
M
MAX
V
t
PHL
M
to the CP input
V
M
t
w
t
V
V
su
CC
CC
M
M
t
V
V
h
= 2.3V TO 2.7V AND
= 3.0V TO 3.6V AND
M
M
t
PLH
n
V
t
REC
or CE input to the CP input
M
V
M
V
M
t
su
SH00155
n
t
h
or CE input
0V
0V
V
0V
3.0V or V
3.0V or V
whichever
whichever
3.0V or V
OH
SH00018
whichever
0V
V
0V
SH00017
is less
is less
OH
is less
CC
CC
CC
8
TEST CIRCUIT
OUTPUT
LOW-to-OFF
OFF-to-LOW
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
nOE INPUT
DEFINITIONS
R
C
R
GENERATOR
SWITCH POSITION
GND
V
V
t
t
V
GND
t
PHZ
L
L
T
PLH
PLZ
V
OL
OH
CC
TEST
PULSE
I
= Load resistor
= Load capacitance includes jig and probe capacitance
= Termination resistance should be equal to Z
Waveform 4. 3-State Enable and Disable Times
of pulse generators.
Waveform 5. Load circuitry for switching times
/t
/t
/t
PHL
PZL
PZH
Test Circuit for 3-State Outputs
SWITCH
2<V
Open
GND
V
outputs
enabled
V
IN
M
t
CC
PLZ
R
t
PHZ
T
D.U.T.
V
V
CC
X
V
Y
2.7 – 3.6V
74ALVCH16823
t 2.7V
V
V
outputs
disabled
OUT
CC
C
L
t
Product specification
PZL
t
PZH
2.7V
V
V
CC
IN
OUT
S
1
R
R
V
L
L
=500
=500
M
V
M
2<V
GND
Open
SW00047
SW00308
outputs
enabled
CC