74ALVCH16374DGG;11 NXP Semiconductors, 74ALVCH16374DGG;11 Datasheet - Page 9

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74ALVCH16374DGG;11

Manufacturer Part Number
74ALVCH16374DGG;11
Description
74ALVCH16374DGG/TSSOP48/TUBE-B
Manufacturer
NXP Semiconductors
Series
74ALVCHr
Type
D-Type Busr
Datasheet

Specifications of 74ALVCH16374DGG;11

Function
Standard
Output Type
Tri-State Non Inverted
Number Of Elements
2
Number Of Bits Per Element
8
Frequency - Clock
300MHz
Delay Time - Propagation
2.4ns
Trigger Type
Positive Edge
Current - Output High, Low
24mA, 24mA
Voltage - Supply
1.2 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935205130112
NXP Semiconductors
Table 7.
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V); test circuit
[1]
[2]
[3]
[4]
[5]
74ALVCH16374_3
Product data sheet
Symbol
t
t
t
t
C
dis
W
su
h
PD
All typical values are measured at T
Typical values are measured at V
Typical values are measured at V
t
t
t
C
P
f
C
V
N = number of inputs switching;
Σ(C
pd
en
dis
i
D
CC
PD
= input frequency in MHz; f
L
is the same as t
is the same as t
= output load capacitance in pF;
= C
is the same as t
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
× V
PD
Dynamic characteristics
CC
Parameter
disable time
pulse width
set-up time
hold time
power dissipation
capacitance
× V
2
× f
CC
o
2
) = sum of the outputs.
× f
PLH
PZL
PLZ
i
× N + Σ(C
and t
and t
and t
PZH
PHL
PHZ
o
= output frequency in MHz;
L
.
.
.
× V
CC
CC
Conditions
nOE to nQn; see
nCP HIGH or LOW; see
Dn to nCP; see
Dn to nCP; see
per flip-flop; V
CC
amb
= 2.5 V.
= 3.3 V.
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
outputs enabled
outputs disabled
2
…continued
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
× f
= 25 °C.
= 1.2 V
= 1.8 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
= 1.8 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
= 1.8 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
= 1.8 V
= 2.3 V to 2.7 V
= 2.7 V
= 3.0 V to 3.6 V
o
All information provided in this document is subject to legal disclaimers.
) where:
I
= GND to V
Rev. 03 — 27 April 2010
Figure 8
Figure 8
Figure 7
D
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
in μW).
Figure 6
CC
[4]
[2]
[3]
[2]
[3]
[2]
[3]
[2]
[3]
[5]
74ALVCH16374
Min
1.5
1.0
1.0
1.0
4.0
3.0
3.0
2.5
1.5
1.2
1.5
1.2
0.6
0.8
0.6
0.8
-
-
-
Figure
Typ
−0.2
−0.1
−0.2
6.2
3.1
2.1
2.9
2.6
2.0
1.6
1.6
1.4
0.2
0.2
0.4
0.2
0.0
16
10
[1]
© NXP B.V. 2010. All rights reserved.
9.
Max
5.4
4.0
4.5
4.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
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