74ALVCH162244DGG:5 NXP Semiconductors, 74ALVCH162244DGG:5 Datasheet - Page 2

• Manufacturer Part Number: 74ALVCH162244DGG:5
• Description: 74ALVCH162244DGG/TSSOP48/REEL1
• Manufacturer: NXP Semiconductors
• Series: 74ALVCHr

Specifications of 74ALVCH162244DGG:5

• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 4
• Number Of Bits Per Element: 4
• Current - Output High, Low: 12mA, 12mA
• Voltage - Supply: 1.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ALVCH162244DG-T; 74ALVCH162244DG-T; 935205110518

1. C
Philips Semiconductors
FEATURES
DESCRIPTION
The 74ALVCH162244 is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most advanced
CMOS compatible TTL families.
The 74ALVCH162244 is a 16-bit non-inverting buffer/line driver with
3-State outputs. The device can be used as four 4-bit buffers, two
8-bit buffers or one 16-bit buffer. The 3-State outputs are controlled
by the output enable inputs 1OE and 2OE. A HIGH on nOE causes
the outputs to assume a high impedance OFF-state. The
74ALVCH162244 is designed with 30 series resistors in both HIGH
and LOW output states.
The 74ALVCH162244 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
QUICK REFERENCE DATA
GND = 0 V; T
NOTES:
ORDERING INFORMATION
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
1998 Jun 29
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
MULTIBYTE
Low inductance multiple V
and ground bounce
Direct interface with TTL levels
Bus hold on all data inputs
Integrated 30 termination resistor
16-bit buffer/line driver with 30W termination resistor
(3-State)
t
C
C
C
PHL
P
f
SYMBOL
o
I
PD
PD
D
= output frequency in MHz; V
= C
/t
PLH
is used to determine the dynamic power dissipation (P
PD
PACKAGES
amb
TM
V
CC
= 25 C; t
flow-through standard pin-out architecture
Propagation delay
An to Yn
Input capacitance
Power dissipation capacitance per buffer
Power dissipation capacitance per buffer
2
f
i
+ S (C
r
= t
CC
f
L
and ground pins for minimum noise
2.5 ns
PARAMETER
V
CC
CC
= supply voltage in V; S (C
2
TEMPERATURE RANGE
f
o
) where: f
–40 C to +85 C
–40 C to +85 C
i
= input frequency in MHz; C
D
in mW):
L
V
V
V = GND to V
V
CC
CC
I
= GND to V
OUTSIDE NORTH AMERICA
V
CC
= 2.5V, C
= 3.3V, C
74ALVCH162244 DGG
2
2
74ALVCH162244 DL
PIN CONFIGURATION
f
o
) = sum of the outputs.
L
L
CC
CC
= 30pF
= 50pF
1
1
L
CONDITIONS
= output load capacitance in pF;
GND
GND
GND
GND
1OE
4OE
V
2Y0
2Y1
3Y3
V
4Y0
4Y2
4Y3
1Y0
1Y1
1Y2
1Y3
2Y2
2Y3
3Y0
3Y1
3Y2
4Y1
CC
CC
Outputs disabled
Outputs enabled
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
NORTH AMERICA
ACH162244 DGG
ACH162244 DL
74ALVCH162244
SW00194
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
TYPICAL
2OE
1A0
1A1
GND
1A2
1A3
V
2A0
2A1
GND
2A2
2A3
3A0
3A1
GND
3A2
3A3
V
4A0
4A1
GND
4A2
4A3
3OE
Product specification
CC
CC
3.0
2.7
5.0
25
4
DWG NUMBER
853-2084 19638
SOT370-1
SOT362-1
UNIT
pF
pF
pF
ns