CY7C1021D-10ZSXIT Cypress Semiconductor Corp, CY7C1021D-10ZSXIT Datasheet - Page 6

• Manufacturer Part Number: CY7C1021D-10ZSXIT
• Description: CY7C1021D-10ZSXIT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1021D-10ZSXIT

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 1M (64K x 16)
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TSOP II
• Memory Configuration: 64K X 16
• Access Time: 10ns
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: TSOP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range
Document #: 38-05462 Rev. *J
Notes
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Parameter
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
BW
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I
6. t
7. At any given temperature and voltage condition, t
8. t
9. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write, and
and 30-pF load capacitance.
state.
the transition of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates
the write.
POWER
HZOE
[6]
, t
HZBE
gives the minimum amount of time that the power supply should be at typical V
[5]
, t
[9]
HZCE
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
Byte Enable to End of Write
CC
, and t
(typical) to the first access
HZWE
are specified with a load capacitance of 5 pF as in (c) of
[7]
[7]
[7, 8]
[7, 8]
[7]
[7, 8]
HZCE
is less than t
Description
LZCE
, t
HZOE
is less than t
Figure 2 on page
CC
LZOE
values until the first memory access can be performed.
, and t
HZWE
5. Transition is measured when the outputs enter a high impedance
is less than t
LZWE
for any given device.
Min
100
-10 (Industrial)
10
10
–
3
–
–
0
–
3
–
0
–
–
0
–
7
7
0
0
7
6
0
3
–
7
CY7C1021D
Max
10
10
10
–
–
–
5
–
5
–
5
–
5
–
5
–
–
–
–
–
–
–
–
–
5
–
Page 6 of 16
OL
Unit
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/I
OH
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