5M160ZE64C5N Altera, 5M160ZE64C5N Datasheet - Page 157
5M160ZE64C5N
Manufacturer Part Number
5M160ZE64C5N
Description
ALTERA
Manufacturer
Altera
Series
MAX Vr
Datasheets
1.DK-DEV-5M570ZN.pdf
(30 pages)
2.DK-DEV-5M570ZN.pdf
(164 pages)
3.DK-DSP-3SL150N.pdf
(80 pages)
Specifications of 5M160ZE64C5N
Cpld Type
FLASH
No. Of Macrocells
128
No. Of I/o's
79
Propagation Delay
7.5ns
Global Clock Setup Time
4.6ns
Frequency
118.3MHz
Supply Voltage Range
1.71V To 1.89V
Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
1.71 V ~ 1.89 V
Number Of Logic Elements/blocks
160
Number Of Macrocells
128
Number Of Gates
-
Number Of I /o
54
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP Exposed Pad
Rohs Compliant
Yes
Lead Free Status / Rohs Status
Vendor undefined / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
5M160ZE64C5N
Manufacturer:
MAXIM
Quantity:
11 540
Company:
Part Number:
5M160ZE64C5N
Manufacturer:
ALTERA
Quantity:
100
Part Number:
5M160ZE64C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Chapter 8: JTAG Boundary-Scan Testing in MAX V Devices
IEEE Std. 1149.1 BST Operation Control
Figure 8–10. IEEE Std. 1149.1 BST EXTEST Mode
December 2010 Altera Corporation
Figure 8–10
OUTJ
OUTJ
OEJ
OEJ
INJ
INJ
SHIFT
SHIFT
SDI
SDI
shows the capture, shift, and update phases of EXTEST mode.
0
1
0
1
0
1
0
1
0
1
0
1
CLOCK
CLOCK
D
D
D
D
D
D
Output
Output
Input
Input
OE
OE
Q
Q
Q
Q
Q
Q
(Shift and Update Phase)
SDO
SDO
Capture
Registers
Capture
Registers
(Capture Phase)
UPDATE
UPDATE
D
D
D
D
Output
Output
OE
OE
Q
Q
Q
Q
Update
Registers
Update
Registers
HIGHZ
HIGHZ
0
1
0
1
MODE
MODE
0
1
0
1
0
1
0
1
Global Signals
Global Signals
PIN_IN
PIN_OE
PIN_OUT
PIN_IN
PIN_OE
PIN_OUT
Output
Buffer
Output
Buffer
Pin
Pin
MAX V Device Handbook
8–11