5M160ZE64C5N Altera, 5M160ZE64C5N Datasheet - Page 132

• Manufacturer Part Number: 5M160ZE64C5N
• Description: ALTERA
• Manufacturer: Altera
• Series: MAX Vr

Specifications of 5M160ZE64C5N

• Cpld Type: FLASH
• No. Of Macrocells: 128
• No. Of I/o's: 79
• Propagation Delay: 7.5ns
• Global Clock Setup Time: 4.6ns
• Frequency: 118.3MHz
• Supply Voltage Range: 1.71V To 1.89V
• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 7.5ns
• Voltage Supply - Internal: 1.71 V ~ 1.89 V
• Number Of Logic Elements/blocks: 160
• Number Of Macrocells: 128
• Number Of Gates: -
• Number Of I /o: 54
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP Exposed Pad
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Vendor undefined / RoHS Compliant

7–30
MAX V Device Handbook
UFM-ERASE
The UFM-ERASE (CE) instruction erases both UFM sector 0 and sector 1 for SPI
Extended Mode. While for SPI Base mode, the CE instruction has the same
functionality as the SECTOR-ERASE (SE) instruction, which erases UFM sector 0 only.
WEN bit and the UFM sectors must not be protected for CE operation to be successful.
nCS must be driven high before the instruction is executed internally. You may poll the
nRDY bit in the software status register for the completion of the internal self-timed CE
cycle. For both SPI Extended mode and Base mode, the CE operation is performed in
the following sequence as shown in
1. nCS is pulled low.
2. Opcode 01100000 is transmitted into the interface.
3. nCS is pulled back to high.
Figure 7–27
Figure 7–27. UFM-ERASE Operation Sequence
shows the UFM-ERASE operation sequence.
SCK
nCS
SI
SO
MSB
0
1
Figure
Instruction
2
8-bit
60
3
H
4
7–27:
5 6 7
High Impedance
Chapter 7: User Flash Memory in MAX V Devices
January 2011 Altera Corporation
Software Support for UFM Block