LFE2-50E-D-EVN Lattice, LFE2-50E-D-EVN Datasheet - Page 2

• Manufacturer Part Number: LFE2-50E-D-EVN
• Description: MCU, MPU & DSP Development Tools LatticeMico32/DSP DEV BD/LatticeECP2
• Manufacturer: Lattice

Specifications of LFE2-50E-D-EVN

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Introduction
This document describes the features and functionality of the LatticeMico32™/DSP Development Board for
LatticeECP2™ devices. This board is designed as a hardware platform for design and development with the
LatticeMico32 microprocessor, as well as for the LatticeMico8™ microcontroller, and for various DSP functions.
Note: There are two versions of this board, named version 1 (v1) and version 2 (v2). Differences between the v1
and v2 boards are described in this document as required. The appendices of this document contain schematics of
both versions. In summary, v2 boards include the following changes:
• Copper plating indicates v2 in text (HPEminiv2)
• A pushbutton has been added for USB reset. This allows the FPGA to be reset independently from the USB
• Boards are populated with a MachXO-2280 device (v1 boards were populated with a MachXO-640).
• Board color is blue, and board is fully RoHS compliant.
This document describes the numerous functional elements of the board. The schematics of the board can be
found in the appendices at the end of this document.
Features
• Lattice ECP2-50 FPGA with 48 kLUTs, 387 kbit of Embedded Block RAM, 18 sysDSP™ blocks, 72 18x18 multi-
• Lattice MachXO™ with 640 LUTs and 6.1 kbit of RAM
• Serial Flash with at least 8 Mbit for non-volatile storage of FPGA configuration data.
• DDR SODIMM socket for DDR SDRAM modules (DDR1, 100-133MHz, 32-bit data bus)
• Parallel Flash 2x128 Mbit, organized as 8M 32-bit words
• SRAM 2x4 Mbit, organized as 256K 32-bit words
• USB 2.0 connector and integrated ispDOWNLOAD
• Flywire connector for programming using an ispDOWNLOAD cable (available separately)
• 9-pin RS232 serial port (230 Kbps)
• 15-pin VGA (64 color encoding)
• Ethernet 10/100 M full/half duplex
• Two USB 2.0 compatible host connectors
• One USB 2.0 compatible target connector
• One USB OTG (On-the-Go) connector
• Expansion connector with 46 user I/Os
• 12x12 prototyping area for the integration of individual components (connections to the FPGA)
• Sigma Delta D/A converter
• Two SATA interfaces with four LVDS signal pairs for high-speed data transfer (Note: Full SATA implementation is
• AC’97 Stereo Audio Codec with line input and output
• LCD connector for character displays, with contrast potentiometer
• 25 MHz oscillator with clock distribution buffer
Cable circuitry.
pliers, 6 PLLs, and 500 user I/O pins
not supported)
®
cable for JTAG programming the FPGA
2
LatticeMico32/DSP Development Board
for LatticeECP2 User’s Guide