MAX1385EVC16 Maxim Integrated Products, MAX1385EVC16 Datasheet - Page 42

• Manufacturer Part Number: MAX1385EVC16
• Description: Power Management Modules & Development Tools EVALUATION KIT FOR T FOR THE MAX1385BETM+
• Manufacturer: Maxim Integrated Products

Specifications of MAX1385EVC16

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual RF LDMOS Bias Controllers
with I
Data transfers are acknowledged with an acknowledge
bit (ACK) or a not-acknowledge bit (NACK). Both the
master and the MAX1385/MAX1386 generate ACK bits.
To generate an ACK, SDA must be pulled low before
the rising edge of the ninth clock pulse and kept low
during the high period of the ninth clock pulse (see
Figure 20). To generate a NACK, SDA is pulled high
before the rising edge of the ninth clock pulse and is
left high for the duration of the ninth clock pulse.
Figure 12. Write/Readback Sequence
Figure 13. Read-Modify-Write Sequence
Figure 14. Slave Address Byte
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______________________________________________________________________________________
SDA
SCL
S OR Sr
2
C/SPI Interface
S
S OR Sr
ADDRESS
Sr
Sr
7 BITS
ADDRESS
ADDRESS
ADDRESS
0
1
7 BITS
7 BITS
7 BITS
R/W
0
ACK
2
1
Acknowledge Bits
R/W
R/W
R/W
0
0
COMMAND
1
8 BITS
READ
ACK
ACK
ACK
0
3
ACK
COMMAND
COMMAND
8 BITS (MSB)
WRITE
WRITE
8 BITS
8 BITS
DATA
Sr
4
0
ADDRESS
7 BITS
ACK
ACK
ACK
A2
Monitoring NACK bits allow for detection of unsuccess-
ful data transfers. NACK bits can also be used by the
master to interrupt the current data transfer to start
another data transfer. The MAX1385/MAX1386 do not
issue an ACK after the last byte of a full reset write to
the Software Clear register.
At power-up, the bus timing is set for slow-/fast-speed
mode (FS mode), which allows bus speeds up to
400kHz. The MAX1385/MAX1386 are configurable for
5
R/W
8 BITS (MSB)
1
8 BITS (MSB)
8 BITS (LSB)
DATA
DATA
DATA
ACK
A1
6
8 BITS (MSB)
DATA
NACK
ACK
ACK
A0
7
Sr OR P
8 BITS (LSB)
ACK
8 BITS (LSB)
DATA
DATA
R/W
8
8 BITS (LSB)
DATA
Fast/High-Speed Modes
ACK
ACK
ACK
9
NACK
Sr OR P