MAX1385EVC16 Maxim Integrated Products, MAX1385EVC16 Datasheet - Page 39

• Manufacturer Part Number: MAX1385EVC16
• Description: Power Management Modules & Development Tools EVALUATION KIT FOR T FOR THE MAX1385BETM+
• Manufacturer: Maxim Integrated Products

Specifications of MAX1385EVC16

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16 bits of data from a MAX1385/MAX1386 register (see
Figure 11):
1) After generating a START condition (S or Sr),
2) Send the appropriate read command byte (see the
3) After generating a repeated START condition (Sr),
4) The MAX1385/MAX1386 transmit the most signifi-
5) The MAX1385/MAX1386 transmit the least signifi-
Table 23. FIFO (Read)
D15
address the MAX1385/MAX1386 by sending the
appropriate slave address byte and its correspond-
ing R/W bit set to a 0 (see the Slave Address Byte
section). The MAX1385/MAX1386 then answer with
an ACK bit (see the Acknowledge Bits section).
Command Byte section). The MAX1385/MAX1386
answer with an ACK bit.
address the MAX1385/MAX1386 once more by
sending the appropriate slave address byte and its
R/W bit set to 1. The MAX1385/MAX1386 answer
with an ACK bit.
cant 8-bit data byte of the 16-bit data word with the
MSB first. Afterwards, the master needs to send an
ACK bit.
cant 8-bit byte of the 16-bit word with the MSB first.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D14
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
______________________________________________________________________________________
D13
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DATA BITS
D12
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Dual RF LDMOS Bias Controllers
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
D11
—
—
—
—
—
—
—
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
D0
—
—
—
—
—
—
—
6) The master issues a NACK bit and then generates a
Continue to poll the current register or read multiple
words (e.g., empty FIFO of several conversion results)
by omitting step 6 and keep issuing ACK bits after each
data byte. Use the following 3-byte sequence to read
16 bits of data from the last accessed MAX1385/
MAX1386 register:
1) After generating a START condition (S or Sr),
Table 24. RDFINE1 and RDFINE2 (Read)
DATA BITS
with I
D15–D10
repeated START or STOP condition (Sr or P).
address the MAX1385/MAX1386 by sending the
appropriate 7-bit slave address byte and its corre-
sponding R/W bit set to 1 (see the Slave Address
Byte section). The MAX1385/MAX1386 then answer
with an ACK bit (see the Acknowledge Bits section).
D9–D0
Internal temperature sensor
Channel 1 external temperature
Channel 1 drain current (PGAOUT1)
ADCIN1
Channel 2 external temperature
Channel 2 drain current (PGAOUT2)
ADCIN2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Conversion may be corrupted. This occurs only when
arriving data causes the FIFO to overflow at the same time
data is being read out.
Empty FIFO. The current value of the Flag register is
provided in place of the FIFO data.
00 0000 0000
2
POR
C/SPI Interface
CONVERSION ORIGIN
X
Don’t care.
10-bit fine DAC input code.
D9 is the MSB.
FUNCTION
39