71M6521FEIM-DB Maxim Integrated Products, 71M6521FEIM-DB Datasheet - Page 50

• Manufacturer Part Number: 71M6521FEIM-DB
• Description: Power Management Modules & Development Tools 71M6521FE DEMO BOARD M6521FE DEMO BOARD
• Manufacturer: Maxim Integrated Products

Specifications of 71M6521FEIM-DB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

There are total 12 interrupts available for the 80515, and the revision 4.7a Demo Code uses a total of 11 interrupts.
Table 5-10 shows the interrupt service routines (ISRs), the corresponding vectors (Table 6-58 in section 6.3.5.4) and
their priority, as assigned by the MPU using the IP0 and IP1 registers (see section 6.3.5.2).
In general, a higher priority interrupt can preempt lower-priority interrupt code. The interrupt priority hardware is
controlled by two registers, IP and IP1 (named IPL and IPH in the demo code). The MPU supports four priorities, and a
fifth is possible with a small amount of software support.
The best practice is to set priorities once, near the start of initialization. Setting priorities dynamically while interrupts
occur can have undefined results. Since some of the interrupts detect power failures that can occur at any time,
changing interrupt priorities in the middle of the code is not recommended.
In the 6521 demo code, interrupt priorities are set higher for urgent tasks. Among equally-urgent tasks, priorities are set
higher for faster interrupts. The following describes interrupt priorities for the version 4.3.3 of the Demo Code:
The priority is set once, in main_init() of main\Main.c. It is also cleared to 0s in the soft reset routine, but this is followed
by logic that calls four RTIs to reset the interrupt acknowledge logic for all four hardware interrupt levels. The system
priority value is assembled from constants in Main\options_gbl.h. The constants are defined in Util\priority2x.h.
The highest priority interrupt group are the PLL_OK interrupt (external interrupt 4, see Main\batmodes_20.c), and timer
1.
shares the same priority bits, and is currently unused (sample code is in Io\tmr1.c, &.h), though earlier versions used it
to set the real-time-clock.
The high-priority interrupt group is used for CE_BUSY (external interrupt 3, see Meter\ce.c), pulse counting (external
interrupts 0 and 1, Meter\pcnt.c) and Serial 1 (Io\ser1.c&.h). External interrupt 3 and 1 share priority bits, as does
external interrupt 0 and serial 1. CE_BUSY is urgent because it occasionally reads the CE's status to detect sag. The
pulse counting interrupts are less urgent, but they are small and run very quickly. Serial 1 is intended for AMR, so
making its interrupts high priority should help its data transfer timing to be more reliable.
The low priority group contains Serial 0 and Timer 0. These can generally wait a millisecond, and if necessary, can
afford to miss fast interrupts. Serial 0 is the command line interface (See the directory Cli), and Timer 0 is run at a 10
millisecond interval as the timebase for the software timers (Util\tmr.c, Io\tmr0.c&.h). Serial 0 shares its priority bits with
Revision 1.7
5.4.2 Foreground
Interrupt Source
Pulse count
Pulse count
Flash-Write collision
fwcol0
Flash-Write collision
fwcol1
CE Busy
Power fail/power return
EEPROM
XFER busy
RTC
Timer0
Timer1
UART 0
UART 1
PLL_OK is urgent because it indicates power supply failure, and the software must start battery modes. Timer 1
Interrupt Service
Routine
pcnt_w_isr()
pcnt_v_isr()
fwcol_isr()
fwcol_isr()
ce_busyz_int()
pll_isr()
eeprom_isr()
ce_xfer_busyz_rtc_int()
rtc_isr()
tmr0_isr()
tmr1_isr()
es0_isr
es1_isr
© Copyright 2005-2007 TERIDIAN Semiconductor Corporation
Table 5-10: Interrupt Service Routines
TERIDIAN Proprietary
EXT6 (shared
EXT6 (shared
External or
w/ XFER)
Interrupt
Internal
w/ RTC)
EXT0
EXT1
EXT2
EXT2
EXT3
EXT4
EXT5
batmodes_20.c
In source file
eeprom.c
serial.c
serial.c
flash.c
flash.c
tmr0.c
tmr1.c
pcnt.c
pcnt.c
71M652X Software User’s Guide
rtc.c
ce.c
ce.c
Vector
0x03
0x13
0x4B
0x4B
0x53
0x5B
0x63
0x6B
0x6B
0x0B
0x1B
0x23
0x83
highest)
50 of 138
Priority
(3 =
0
3
0
0
3
3
0
2
2
0
3
0
0