SI9166DB Vishay, SI9166DB Datasheet - Page 8

• Manufacturer Part Number: SI9166DB
• Description: Power Management Modules & Development Tools SI9166 Demo Board
• Manufacturer: Vishay

Specifications of SI9166DB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si9166
Vishay Siliconix
Oscillator
The oscillator is designed to operate up to 2-MHz minimal. The
2-MHz operating frequency allows the converter to minimize
the inductor and capacitor size, improving the power density
of the converter.
quiescent current is only 500 mA with unique power saving
circuit design. The switching frequency is easily programmed
by attaching resistor to R
versus R
desired operating frequency. The tolerance on the operating
frequency is (20% with 1% tolerance resistor).
Synchronization
The synchronization to external clock is easily accomplished
by connecting the external clock into the SYNC pin. The logic
high-to-low transition synchronizes the clock. The external
clock frequency must be within 1.2 to 1.5 times the internal
clock frequency.
Break-Before-Make Timing
A proper BBM time is essential in order to prevent
shoot-through current and to maintain high efficiency. The
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8
OSC
curve to select the proper timing values for
Even with 2-MHz switching frequency,
OSC
pin. See oscillator frequency
break-before-make time is set internally at 20 to 60 ns @
V
monitored and when the gate to source voltage reaches
1.75 V above or below the initial starting voltage, 20 to 60 ns
BBM time is set before the other gate drive transitions to its
proper state. The maximum and minimum duty cycle is limited
by the BBM time. Since the BBM time is fixed, controllable
maximum duty cycle will vary depending on the switching
frequency.
Output Driver Stage
The DH pin is designed to drive the high-side p-channel
MOSFET, independent of topology. The DL pin is designed to
drive the low-side n-channel MOSFET, independent of
topology. The driver stage is sized to sink and source peak
currents up to 450 mA with V
gate drive output trace inductance can produce negative
voltage on the DH and DL respect to PGND. The gate drive
circuit is capable of withstanding these negative voltages
without any functional defects.
S
= 3.6 V. The high- and low-side gate drive voltages are
S
= 3.3 V. The ringing from the
S-40701—Rev. C, 19-Apr-04
Document Number: 70847