SI9166DB Vishay, SI9166DB Datasheet - Page 6

• Manufacturer Part Number: SI9166DB
• Description: Power Management Modules & Development Tools SI9166 Demo Board
• Manufacturer: Vishay

Specifications of SI9166DB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si9166
Vishay Siliconix
DETAIL OPERATIONAL DESCRIPTION
Start-Up
The UVLO circuit prevents the controller output driver and
oscillator circuit from turning on, if the voltage on V
than 2.5 V. With typical UVLO hysteresis of 0.1 V, controller is
continuously powered on until the V
2.4 V. This hysteresis prevents the converter from oscillating
during the start-up phase and unintentionally locking up the
system. Once the V
and with no other shutdown condition detected, an internal
power-on-reset timer is activated while most circuitry, except
the output driver, are turned on. After the POR time-out of
about 1 ms, the internal soft-start capacitor is allowed to
charge. When the soft-start capacitor voltage reaches 0.5 V,
the PWM circuit is enabled. Thereafter, the constant current
charging the soft-start capacitor will force the converter output
voltage to rise gradually without overshooting. To prevent
negative undershoot, the synchronous switch is tri-stated until
the duty cycle reaches about 10%.
diagram. In tri-state, the high-side p-channel MOSFET is
turned off by pulling up the gate voltage (DH) to V
The low-side n-channel MOSFET is turned off by pulling down
the gate voltage (DL) to PGND potential. Note that the Si9166
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6
FUNCTIONAL BLOCK DIAGRAM
PWM/PSM
COMP
MODE
SYNC
R
V
OSC
REF
FB
V
O
DD
C
OSC
Reference
Generator
Threshold
Oscillator
voltage exceeds the UVLO threshold,
1.3 V
DD
voltage drops below
See start-up timing
Ramp
1.0 V
Soft-Start
Timer
DD
S
pin is less
potential.
0.5 V
V
DD
Positive
Supply
Modulator
Modulator
UVLO
PWM
will always soft start in the PWM mode regardless of the
voltage level on the PWM/PSM pin.
Shutdown
The Si9166 is designed to conserve battery life by decreasing
current consumption of IC during normal operation as well as
the shutdown mode. With logic low-level on the SD pin, current
consumption of the Si9166 decreases to less than 1 mA by
shutting off most of the circuits. The logic high enables the
controller and starts up as described in Start-Up section
above.
MODE Selection
The Si9166 can be programmed to operate as Buck or Boost
converter. If the MODE pin is connected to AGND, it operates
in buck mode. If the MODE pin is connected to V
in boost mode. The DH gate drive output is designed to drive
high-side p-channel MOSFET, acting as the main switch in
buck topology and the synchronous rectifier in boost topology.
The DL gate drive output is designed to drive low-side
n-channel MOSFET, acting as the synchronous rectifier in
buck topology and the main switch in boost topology.
PSM
SYSTEM MONITOR
POR
SD
PWM/PSM
PWM
PSM
Select
EN
EN
Generator
Bias
PWM
PSM
GND
Drivers
IN
IN
Negative
Return and
Substrate
S-40701—Rev. C, 19-Apr-04
Document Number: 70847
DD
V
DH
DL
PGND
, it operates
S