CRD-5378 Cirrus Logic Inc, CRD-5378 Datasheet - Page 20

• Manufacturer Part Number: CRD-5378
• Description: Audio Modules & Development Tools Ref Bd LP Sngl-Ch Decimation Filter
• Manufacturer: Cirrus Logic Inc

Specifications of CRD-5378

• Description/function: Audio D/A
• Operating Supply Voltage: 3.3 V
• Product: Audio Modules
• Supply Current: 100 mA
• For Use With/related Products: CS3302A, CS5373A, CS5378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Amplifier, modulator and test DAC pin settings are controlled through the GPIO port.
2.3.1.1
Immediately following the reset signal rising edge, the CS5378 digital filter latches the states of the
GPIO[4..6]:PLL[0..2] and GPIO7:BOOT pins. The reset states of the GPIO[4..6]:PLL[0..2] pins select the
master clock input frequency and type, while the reset state of the GPIO7:BOOT pin selects how the
CS5378 digital filter receives configuration data.
At reset, the CS5378 digital filter GPIO pins default as inputs with weak pull-up resistors enabled. There-
fore, if left floating, the GPIO state will read high upon reset.
The CRD5378 provides the option to connect the GPIO[4..6]:PLL[0..2] and GPIO7:BOOT pins to 10k Ω
pull-down resistors (R15, R41, and R42) so they will read low at reset. Because the pin states are latched
only during reset, GPIO pins can be programmed and used normally after reset without affecting the PLL
and BOOT selections.
Detailed information about the PLL input clock and BOOT mode selections at reset can be found in the
CS5378 data sheet.
2.3.1.2
On CRD5378, configuration of the digital filter is through the SPI port by the on-board 8051 microcontrol-
ler, which receives commands from the PC evaluation software via the USB interface. Evaluation software
commands can write/read digital filter registers, specify digital filter coefficients and start/stop digital filter
operation.
By default the BOOT signal is set low to indicate configuration information is written by the microcontroller.
2.3.1.3
To make synchronous analog measurements throughout a distributed system, a synchronous system
clock needs to be provided to each measurement node. For evaluation testing purposes, the CRD5378
can receive an external system clock by access through J1 and by non-population of R2, R3, R4, R60,
and R70. With this external clock, a synchronous local clock can be created using the CS5378 PLL. The
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GPIO Signals
GPIO[0]:MUX[0]
GPIO[1..3]:MODE[0..2]
GPIO[4..6]:GAIN[0..2]
GPIO[7]:MUX[1]
Reset Options - BOOT, PLL
Configuration - SPI Port
Phase Locked Loop
Description
Amplifier input mux selection
Test DAC mode selection
Amplifier gain / test DAC attenuation
Amplifier input mux selection
CRD5378
DS639RD2