TEA1750T/N1/DG,518 NXP Semiconductors, TEA1750T/N1/DG,518 Datasheet - Page 10
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TEA1750T/N1/DG,518
Manufacturer Part Number
TEA1750T/N1/DG,518
Description
IC PFC CONTROLLER 16SO
Manufacturer
NXP Semiconductors
Series
GreenChip™ IIIr
Datasheet
1.TEA1750TN1518.pdf
(29 pages)
Specifications of TEA1750T/N1/DG,518
Mode
Discontinuous Conduction (DCM)
Frequency - Switching
100kHz ~ 150kHz
Current - Startup
60µA
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.154", 3.90mm Width)
Output Voltage
12 V
Output Current
- 80 uA
Output Power
0.6 W
Duty Cycle (max)
10 %
Input Voltage
70 VAC to 276 VAC
Switching Frequency
125 KHz
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply
-
Operating Temperature
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TEA1750T/N1/DG,518
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
TEA1750_2
Product data sheet
7.2.6 Burst mode control
When the output power of the flyback converter (see
converter switches over to frequency reduction mode. When frequency reduction mode is
entered by the flyback controller, the power factor correction circuit switches to burst mode
control.
In burst mode control, switching of the power factor correction circuit is inhibited until the
voltage on the VOSENSE pin has dropped to V
soft-start to avoid audible noise (see
VOSENSE pin reaches V
noise. During the soft-stop time the output voltage of the power factor correction circuit
overshoots, depending on the soft-start resistor and capacitor, R
PFCSENSE pin. As the V
output voltage does not reach the normal operation output voltage of the power factor
correction circuit in a typical application due to this overshoot.
The burst mode repetition rate is defined by the output power and the value of the bus
capacitor, C
During burst mode operation the PFCCOMP pin is clamped between a voltage of
2.7 V (typ) and 3.9 V (typ). The lower clamp voltage limits the maximum power that is
delivered during burst mode operation and yields a more sinusoidal input current during
the burst pulse. The upper clamp voltage ensures that the PFC can return to its normal
regulation point in a limited amount of time when returning from burst mode.
As soon as the flyback converter leaves frequency reduction mode, the power factor
correction circuit restores normal operation. To prevent continuous on and off switching of
the PFC circuit, a small hysteresis is built in (50 mV (typ) on the FBCTRL pin).
Fig 5.
Soft start-up and soft stop of PFC
bus
.
Rev. 02 — 15 December 2008
R SENSE1
S1
R SS1
C SS1
burst(H)
burst(H)
the soft-stop circuit is activated, again to avoid audible
voltage is well below the V
11
PFCSENSE
I start(soft)PFC
Section
7.2.5). As soon as the voltage on the
60 A
+
0.5 V
burst(L)
SOFT START
SOFT STOP
CONTROL
OCP
Section
. Switching then restarts with a
GreenChip III SMPS control IC
reg(VOSENSE)
7.3) is low, the flyback
014aaa018
SS1
and C
TEA1750
© NXP B.V. 2008. All rights reserved.
voltage, the PFC
SS1,
on the
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