A4987SESTR-T Allegro Microsystems Inc, A4987SESTR-T Datasheet - Page 7

• Manufacturer Part Number: A4987SESTR-T
• Description: IC STEPPER MOTOR DRIVER 24QFN
• Manufacturer: Allegro Microsystems Inc

Specifications of A4987SESTR-T

• Applications: Stepper Motor Driver, 2 Phase
• Number Of Outputs: 1
• Current - Output: *
• Voltage - Load: 8 V ~ 35 V
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-WFQFN Exposed Pad
• Motor Type: Stepper
• No. Of Outputs: 2
• Output Current: 1A
• Output Voltage: 35V
• Supply Voltage Range: 3V To 5.5V
• Driver Case Style: QFN
• No. Of Pins: 24
• Operating Temperature Range: -20°C To +85°C
• Evaluation Tools: Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 620-1375 - Board Eval Motor Control A4987
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A4987
Charge Pump
generate a gate supply greater than that of VBB for driving the
source-side FET gates. A 0.1 μF ceramic capacitor, should be
connected between CP1 and CP2. In addition, a 0.1 μF ceramic
capacitor is required between VCP and VBB, to act as a reservoir
for operating the high-side FET gates.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
V
operate the sink-side FET outputs. The nominal output voltage
of the VREG terminal is 7 V. The VREG pin must be decoupled
with a 0.22 μF ceramic capacitor to ground. V
monitored. In the case of a fault condition, the FET outputs of the
A4987 are disabled.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
Shutdown.
or an undervoltage (on VCP), the FET outputs of the A4987 are
disabled until the fault condition is removed. At power-on, the
UVLO (undervoltage lockout) circuit disables the FET outputs
and resets the translator to the Home state.
Sleep Mode
when the motor is not in use, this input disables much of the
internal circuitry including the output FETs, current regulator, and
charge pump. A logic low on the S ¯ ¯ L ¯ ¯ E ¯ ¯ E ¯ ¯ P ¯ pin puts the A4987 into
Sleep mode. When emerging from Sleep mode, in order to allow
the charge pump to stabilize, provide a delay of 1 ms before issu-
ing a logic command.
Mixed Decay Operation.
Decay mode, as shown in figures 5 through 7. As the trip point
is reached, the A4987 initially goes into a fast decay mode for
31.25% of the off-time, t
mode for the remainder of t
appears in figure 4.
Synchronous Rectification
triggered by an internal fixed-off time cycle, load current recir-
culates in Mixed Decay mode. This synchronous rectification
feature turns on the appropriate FETs during current decay, and
effectively shorts out the body diodes with the low FET R
This reduces power dissipation significantly, and can eliminate
the need for external Schottky diodes in many applications. Syn-
chronous rectification turns off when the load current approaches
zero (0 A), preventing reversal of the load current.
REG
(VREG)
In the event of a fault, overtemperature (excess T
.
( ¯ S ¯ ¯ L ¯ ¯ E ¯ ¯ E ¯ ¯ P ¯ ). To minimize power consumption
This internally-generated voltage is used to
(CP1 and CP2). The charge pump is used to
OFF
OFF
. After that, it switches to Slow Decay
. A timing diagram for this feature
The bridge operates in Mixed
. When a PWM-off cycle is
DMOS Dual Full-Bridge PWM Motor Driver
REG
is internally
DS(ON)
J
.
)
Figure 1. Short-to-ground event
Figure 2. Shorted load (OUTxA → OUTxB) in
Slow decay mode
Figure 3. Shorted load (OUTxA → OUTxB) in Mixed decay mode
With Overcurrent Protection
5 A / div.
5 A / div.
5 A / div.
Fast decay portion
(direction change)
Fixed off-time
Fixed off-time
115 Northeast Cutoff, Box 15036
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 [phone]
www.allegromicro.com
t →
t →
t →
Fault latched
7