ADNS-6010 Avago Technologies US Inc., ADNS-6010 Datasheet - Page 12

• Manufacturer Part Number: ADNS-6010
• Description: Optical Sensors - Board Mount Laser mouse sensor
• Manufacturer: Avago Technologies US Inc.

Specifications of ADNS-6010

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, V
12
Parameter
VDD to RESET
Data delay after
RESET
Input delay after
reset
Power Down
Wake from NPD
Data delay after
NPD
RESET pulse width
MISO rise time
MISO fall time
MISO delay after
SCLK
MISO hold time
MOSI hold time
MOSI setup time
SPI time between
write commands
SPI time between
write and read
commands
SPI time between
read and subse-
quent commands
SPI read address-
data delay
SPI motion read
address-data
delay
NCS to SCLK active t
SCLK to NCS inac-
tive
NCS to MISO
high-Z
PROM download
and frame capture
byte-to-byte delay
NCS to burst
mode exit
Transient Supply
Current
Input Capacitance
Symbol
t
t
T
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
I
C
DDT
OP
PU-RESET
PD
PUPD
COMPUTE
PW-RESET
r-MISO
f-MISO
DLY-MISO
hold-MISO
hold-MOSI
setup-MOSI
SWW
SWR
SRW
SRAD
SRAD-MOT
NCS-SCLK
SCLK-NCS
NCS-MISO
LOAD
BEXIT
IN-RST
IN
t
SRR
Min.
10
250
200
120
50
50
250
50
75
120
120
10
4
Typ.
t
40
40
14-22
COMPUTE
Max.
250
180
550
600
75
3.1
200
200
120
68
250
Units
Ps
ms
Ps
Ps
ms
ms
Ps
ns
ns
ns
ns
ns
ns
Ps
Ps
ns
Ps
Ps
ns
ns
ns
Ps
Ps
mA
pF
Notes
From VDD = 3.0V to RESET sampled
From RESET falling edge to valid motion data at 2000 fps
and shutter bound 20k.
From RESET falling edge to inputs active (NPD, MOSI,
NCS, SCLK)
From NPD falling edge to initiate the power down cycle
at 2000 fps (t
From NPD rising edge to valid motion data at 2000 fps
and shutter bound 20k. Max assumes surface change
while NPD is low
From NPD rising edge to all registers contain data from
new images at 2000 fps (See Figure 11).
C
C
From SCLK falling edge to MISO data valid, no load
conditions
Data held until next falling SCLK edge
Amount of time data is valid after SCLK rising edge
From data valid to SCLK rising edge
From rising SCLK for last bit of the first data byte, to ris-
ing SCLK for last bit of the second data byte.
From rising SCLK for last bit of the first data byte, to ris-
ing SCLK for last bit of the second address byte.
From rising SCLK for last bit of the first data byte, to fall-
ing SCLK for first bit of the second address byte.
From rising SCLK for last bit of the address byte, to
falling SCLK for first bit of data being read. All registers
except Motion & Motion_Burst
From rising SCLK for last bit of the address byte, to fall-
ing SCLK for first bit of data being read. Applies to 0x02
Motion, and 0x50 Motion_Burst, registers
From NCS falling edge to first SCLK rising edge
From last SCLK falling edge to NCS rising edge, for valid
MISO data transfer
From NCS rising edge to MISO high-Z state
(See Figure 24 and 25)
Time NCS must be held high to exit burst mode
Max supply current during a VDD3 ramp from 0 to 3.6 V
OSC_IN, OSC_OUT
L
L
= 50pF
= 50pF
pd
= 1 frame period + 100Ps )
DD3
=3.3V, fclk=24MHz.