CDB5460A Cirrus Logic Inc, CDB5460A Datasheet - Page 26

• Manufacturer Part Number: CDB5460A
• Description: Development Kit
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5460A

• Development Tool Type: Hardware - Eval/Demo Board
• Kit Contents: Evaluation Board And Software
• Mcu Supported Families: CS5460A
• Tool / Board Applications: Power Measurement Solution
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: CS5460A

3.3.3 Application Note AN225
For more information on Auto-boot mode, see the
AN225, “USING THE CS5460A AUTO-BOOT
MODE”.
3.4 Interrupt and Watchdog Timer
3.4.1 Interrupt
The INT pin is used to indicate that an event has
taken place in the CS5460A that (may) need atten-
tion. These events inform the meter system about
operation conditions and internal error conditions.
The INT signal is created by combining the Status
Register with the Mask Register. Whenever a bit in
the Status Register becomes active, and the corre-
sponding bit in the Mask Register is a logic 1, the
INT signal becomes active.
3.4.1.1 Clearing the Status Register
Unlike the other registers, the bits in the Status
Register can only be cleared (set to logic 0). When
a word is written to the Status Register, any 1s in
the word will cause the corresponding bits in the
Status Register to be cleared. The other bits of the
Status Register remain unchanged. This allows the
clearing of particular bits in the register without
having to know the state of the other bits. This
mechanism is designed to facilitate handshaking
and to minimize the risk of losing events that ha-
ven’t been processed yet.
3.4.1.2 Typical use of the INT pin
The steps below show how interrupts can be han-
dled by the on-board MCU.
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Initialization:
Step I0 - All Status bits are cleared by writing
FFFFFF (Hex) into the Status Register.
Step I1 - The conditional bits which will be used
to generate interrupts are then written to logic
1 in the Mask Register.
Step I2 - Enable interrupts.
Interrupt Handler Routine:
Step H0 - Read the Status Register.
Step H1 - Disable all interrupts.
Step H2 - Branch to the proper interrupt service
routine.
3.4.1.3 INT Active State
The behavior of the INT pin is controlled by the SI1
and SI0 bits of the Configuration Register. The pin
can be active low (default), active high, active on a
return to logic 0 (pulse-low), or active on a return to
logic 1 (pulse-high).
If the interrupt output signal format is set for either
active-high or active-low assertion, the interrupt
condition is cleared when the bits of the Status
Register are returned to their inactive state. If the
interrupt output signal format is set for either
pulse-high or pulse-low, note that the duration of
the INT pulse will be at least one MCLK/K cycle, al-
though in some cases the pulse may last for 2
MCLK/K cycles.
3.4.1.4 Exceptions
The IC (Invalid Command) bit of the Status Regis-
ter can only be cleared by performing the port ini-
tialization sequence. This is also the only Status
Register bit that is active low.
To properly clear the WDT (Watch Dog Timer) bit
of the Status Register, first read the Energy Regis-
ter, then clear the bit in the Status Register.
3.4.2 Watch Dog Timer
The Watch Dog Timer (WDT) is provided as a
means of alerting the system that there is a poten-
tial breakdown in communication with the micro-
controller. By allowing the WDT to cause an
interrupt, a controller can be brought back, from
some unknown code space, into the proper code
for processing the data created by the converter.
The time-out is preprogrammed to approximately 5
seconds. The countdown restarts each time the
Energy Register is read. Under typical situations,
the Energy Register is read every second. As a re-
sult, the WDT will not time out. Other applications
that use the watchdog timer will need to ensure
Step H3 - Clear the Status Register by writing
back the value read in step H0.
Step H4 - Re-enable interrupts.
Step H5 - Return from interrupt service routine.
This handshaking procedure insures that any
new interrupts activated between steps H0 and
H3 are not lost (cleared) by step H3.
CS5460A
DS487F4